arm: 96b_stm32_sensor_mez: spi: Enable SPI4
This patch enables SPI4 on the 96Boards STM32 Sensors Mezzanine. SPI4 has been broken out to a Grove Connector on the board. Changes: - Updated board dts to enable spi4 - Updated board Kconfig - Updated board documentation - Update board pinmux - Updated stm32f4 pinmux header file - Updated stm32f401 dtsi - Updated stm32f4 defconfig to enable PORTE GPIO - Added board to spi_loopback test Test: spi_loopback test passed Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
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8 changed files with 53 additions and 4 deletions
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@ -100,6 +100,10 @@
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status = "okay";
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};
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&spi4 {
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status = "okay";
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};
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&timers3 {
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status = "okay";
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@ -59,6 +59,9 @@ config SPI_1
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config SPI_2
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default y
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config SPI_4
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default y
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config SPI_STM32_INTERRUPT
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default y
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@ -42,7 +42,7 @@ Hardware
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- GPIO with external interrupt capability
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- UART
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- I2C (2)
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- SPI (2)
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- SPI (3)
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- I2S (1)
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Supported Features
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@ -125,9 +125,10 @@ I2C2 goes to the Groove connectors and can be used to attach external sensors.
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SPI
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---
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96Boards STM32 Sensor Mezzanine board has 2 SPIs. SPI1 is used in slave mode
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96Boards STM32 Sensor Mezzanine board has 3 SPIs. SPI1 is used in slave mode
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as the communication bus with the AP. SPI2 is used in master mode to control
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the LSM6DS3H sensor. The default SPI mapping is:
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the LSM6DS3H sensor. SPI4 is broken out to Grove Connector J5.
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The default SPI mapping is:
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- SPI1_NSS : PA4
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- SPI1_SCK : PA5
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@ -137,6 +138,10 @@ the LSM6DS3H sensor. The default SPI mapping is:
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- SPI2_SCK : PD3
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- SPI2_MISO : PB14
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- SPI2_MOSI : PB15
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- SPI4_NSS : PE11
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- SPI4_SCK : PE12
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- SPI4_MISO : PE13
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- SPI4_MOSI : PE14
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PWM
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---
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@ -58,6 +58,16 @@ static const struct pin_config pinconf[] = {
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{STM32_PIN_PB14, STM32F4_PINMUX_FUNC_PB14_SPI2_MISO},
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{STM32_PIN_PB15, STM32F4_PINMUX_FUNC_PB15_SPI2_MOSI},
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#endif /* CONFIG_SPI_2 */
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#ifdef CONFIG_SPI_4
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#ifdef CONFIG_SPI_STM32_USE_HW_SS
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{STM32_PIN_PE11, STM32F4_PINMUX_FUNC_PE11_SPI4_NSS |
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STM32_OSPEEDR_VERY_HIGH_SPEED},
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#endif /* CONFIG_SPI_STM32_USE_HW_SS */
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{STM32_PIN_PE12, STM32F4_PINMUX_FUNC_PE12_SPI4_SCK |
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STM32_OSPEEDR_VERY_HIGH_SPEED},
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{STM32_PIN_PE13, STM32F4_PINMUX_FUNC_PE13_SPI4_MISO},
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{STM32_PIN_PE14, STM32F4_PINMUX_FUNC_PE14_SPI4_MOSI},
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#endif /* CONFIG_SPI_4 */
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#ifdef CONFIG_I2S_2
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{STM32_PIN_PC7, STM32F4_PINMUX_FUNC_PC7_I2S2_CK},
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{STM32_PIN_PC1, STM32F4_PINMUX_FUNC_PC1_I2S2_SD},
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@ -448,9 +448,21 @@
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#define STM32F4_PINMUX_FUNC_PE8_UART7_TX \
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(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP)
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#define STM32F4_PINMUX_FUNC_PE11_SPI4_NSS \
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(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
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#define STM32F4_PINMUX_FUNC_PE12_SPI4_SCK \
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(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
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#define STM32F4_PINMUX_FUNC_PE13_SPI4_MISO \
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(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
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#define STM32F4_PINMUX_FUNC_PE13_PWM1_CH3 \
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(STM32_PINMUX_ALT_FUNC_1 | STM32_PUSHPULL_PULLUP)
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#define STM32F4_PINMUX_FUNC_PE14_SPI4_MOSI \
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(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
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/* Port F */
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#define STM32F4_PINMUX_FUNC_PF0_I2C2_SDA \
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(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
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@ -30,6 +30,17 @@
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label = "SPI_3";
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};
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spi4: spi@40013400 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
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interrupts = <84 5>;
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status = "disabled";
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label = "SPI_4";
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};
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i2s2: i2s@40003800 {
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compatible = "st,stm32-i2s";
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#address-cells = <1>;
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@ -14,7 +14,7 @@ config NUM_IRQS
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if GPIO_STM32
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config GPIO_STM32_PORTE
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default n
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default y
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config GPIO_STM32_PORTH
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default n
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@ -0,0 +1,4 @@
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CONFIG_SPI_LOOPBACK_CS_GPIO=y
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CONFIG_SPI_LOOPBACK_CS_CTRL_GPIO_DRV_NAME="GPIOE"
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CONFIG_SPI_LOOPBACK_CS_CTRL_GPIO_PIN=11
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CONFIG_SPI_LOOPBACK_DRV_NAME="SPI_4"
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