drivers: flash_gecko: Add flash driver for SiLabs Gecko SoCs

Tested with SLWSTK6061A / BRD4250B wireless starter kit.

Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
This commit is contained in:
Piotr Mienkowski 2018-08-07 14:11:45 +02:00 committed by Anas Nashif
commit d9e2171aa9
26 changed files with 378 additions and 36 deletions

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@ -52,6 +52,8 @@ The efm32hg_slstk3400 board configuration supports the following hardware featur
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | flash memory |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| USART | on-chip | serial port-polling; |

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@ -50,6 +50,8 @@ The efm32wg_stk3800oard configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | flash memory |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |

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@ -60,6 +60,8 @@ The efr32_slwstk6061a board configuration supports the following hardware featur
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | flash memory |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |

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@ -63,6 +63,8 @@ The efr32mg_sltb004a board configuration supports the following hardware feature
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | flash memory |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |

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@ -8,6 +8,7 @@ zephyr_library_sources_ifdef(CONFIG_FLASH_PAGE_LAYOUT flash_page_layout.c)
zephyr_library_sources_ifdef(CONFIG_USERSPACE flash_handlers.c)
zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_SAM0 flash_sam0.c)
zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_NIOS2_QSPI soc_flash_nios2_qspi.c)
zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_GECKO flash_gecko.c)
if(CONFIG_SOC_SERIES_STM32F0X)
zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_STM32

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@ -85,6 +85,8 @@ config SOC_FLASH_NIOS2_QSPI_DEV_NAME
help
Specify the device name for the QSPI flash driver.
source "drivers/flash/Kconfig.gecko"
source "drivers/flash/Kconfig.qmsi"
source "drivers/flash/Kconfig.stm32"

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@ -0,0 +1,16 @@
# Kconfig - Silicon Labs Gecko flash driver config
#
# Copyright (c) 2018, Piotr Mienkowski
#
# SPDX-License-Identifier: Apache-2.0
config SOC_FLASH_GECKO
bool "Silicon Labs Gecko flash driver"
depends on FLASH && SOC_FAMILY_EXX32
select FLASH_HAS_DRIVER_ENABLED
help
Enable Silicon Labs Gecko series internal flash driver.
if SOC_FLASH_GECKO
endif # SOC_FLASH_GECKO

194
drivers/flash/flash_gecko.c Normal file
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@ -0,0 +1,194 @@
/*
* Copyright (c) 2018, Piotr Mienkowski
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stddef.h>
#include <string.h>
#include <errno.h>
#include <kernel.h>
#include <device.h>
#include <em_msc.h>
#include <flash.h>
#include <soc.h>
#define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
#include <logging/log.h>
LOG_MODULE_REGISTER(flash_gecko);
struct flash_gecko_data {
struct k_sem mutex;
};
#define DEV_NAME(dev) ((dev)->config->name)
#define DEV_DATA(dev) \
((struct flash_gecko_data *const)(dev)->driver_data)
static bool write_range_is_valid(off_t offset, u32_t size);
static bool read_range_is_valid(off_t offset, u32_t size);
static int erase_flash_block(off_t offset, size_t size);
static int flash_gecko_read(struct device *dev, off_t offset, void *data,
size_t size)
{
if (!read_range_is_valid(offset, size)) {
return -EINVAL;
}
if (!size) {
return 0;
}
memcpy(data, (u8_t *)CONFIG_FLASH_BASE_ADDRESS + offset, size);
return 0;
}
static int flash_gecko_write(struct device *dev, off_t offset,
const void *data, size_t size)
{
struct flash_gecko_data *const dev_data = DEV_DATA(dev);
MSC_Status_TypeDef msc_ret;
void *address;
int ret = 0;
if (!write_range_is_valid(offset, size)) {
return -EINVAL;
}
if (!size) {
return 0;
}
k_sem_take(&dev_data->mutex, K_FOREVER);
address = (u8_t *)CONFIG_FLASH_BASE_ADDRESS + offset;
msc_ret = MSC_WriteWord(address, data, size);
if (msc_ret < 0) {
ret = -EIO;
}
k_sem_give(&dev_data->mutex);
return ret;
}
static int flash_gecko_erase(struct device *dev, off_t offset, size_t size)
{
struct flash_gecko_data *const dev_data = DEV_DATA(dev);
int ret;
if (!read_range_is_valid(offset, size)) {
return -EINVAL;
}
if ((offset % FLASH_PAGE_SIZE) != 0) {
LOG_ERR("offset %x: not on a page boundary", offset);
return -EINVAL;
}
if ((size % FLASH_PAGE_SIZE) != 0) {
LOG_ERR("size %x: not multiple of a page size", size);
return -EINVAL;
}
if (!size) {
return 0;
}
k_sem_take(&dev_data->mutex, K_FOREVER);
ret = erase_flash_block(offset, size);
k_sem_give(&dev_data->mutex);
return ret;
}
static int flash_gecko_write_protection(struct device *dev, bool enable)
{
struct flash_gecko_data *const dev_data = DEV_DATA(dev);
int ret = 0;
k_sem_take(&dev_data->mutex, K_FOREVER);
if (enable) {
/* Lock the MSC module. */
MSC->LOCK = 0;
} else {
/* Unlock the MSC module. */
MSC->LOCK = MSC_UNLOCK_CODE;
}
k_sem_give(&dev_data->mutex);
return ret;
}
/* Note:
* - A flash address to write to must be aligned to words.
* - Number of bytes to write must be divisible by 4.
*/
static bool write_range_is_valid(off_t offset, u32_t size)
{
return read_range_is_valid(offset, size)
&& (offset % sizeof(u32_t) == 0)
&& (size % 4 == 0);
}
static bool read_range_is_valid(off_t offset, u32_t size)
{
return (offset + size) <= (CONFIG_FLASH_SIZE * 1024);
}
static int erase_flash_block(off_t offset, size_t size)
{
MSC_Status_TypeDef msc_ret;
void *address;
int ret = 0;
for (off_t tmp = offset; tmp < offset + size; tmp += FLASH_PAGE_SIZE) {
address = (u8_t *)CONFIG_FLASH_BASE_ADDRESS + tmp;
msc_ret = MSC_ErasePage(address);
if (msc_ret < 0) {
ret = -EIO;
break;
}
}
return ret;
}
static int flash_gecko_init(struct device *dev)
{
struct flash_gecko_data *const dev_data = DEV_DATA(dev);
k_sem_init(&dev_data->mutex, 1, 1);
MSC_Init();
/* Lock the MSC module. */
MSC->LOCK = 0;
LOG_INF("Device %s initialized", DEV_NAME(dev));
return 0;
}
static const struct flash_driver_api flash_gecko_driver_api = {
.read = flash_gecko_read,
.write = flash_gecko_write,
.erase = flash_gecko_erase,
.write_protection = flash_gecko_write_protection,
/* FLASH_WRITE_BLOCK_SIZE is extracted from device tree as flash node
* property 'write-block-size'.
*/
.write_block_size = FLASH_WRITE_BLOCK_SIZE,
};
static struct flash_gecko_data flash_gecko_0_data;
DEVICE_AND_API_INIT(flash_gecko_0, FLASH_DEV_NAME,
flash_gecko_init, &flash_gecko_0_data, NULL, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &flash_gecko_driver_api);

View file

@ -12,17 +12,28 @@
};
};
flash0: flash@0 {
compatible = "soc-nv-flash";
label = "FLASH_0";
};
sram0: memory@20000000 {
device_type = "memory";
compatible = "mmio-sram";
};
soc {
flash-controller@400c0000 {
compatible = "silabs,gecko-flash-controller";
label = "FLASH_CTRL";
reg = <0x400c0000 0x5c>;
interrupts = <15 0>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@0 {
compatible = "soc-nv-flash";
label = "FLASH_0";
write-block-size = <4>;
};
};
usart0: usart@4000c000 { /* USART0 */
compatible = "silabs,gecko-usart";
reg = <0x4000c000 0x400>;

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@ -8,11 +8,15 @@
#include <silabs/efm32hg.dtsi>
/ {
flash0: flash@0 {
reg = <0 DT_SIZE_K(64)>;
};
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(8)>;
};
soc {
flash-controller@400c0000 {
flash0: flash@0 {
reg = <0 DT_SIZE_K(64)>;
};
};
};
};

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@ -12,17 +12,28 @@
};
};
flash0: flash@0 {
compatible = "soc-nv-flash";
label = "FLASH_0";
};
sram0: memory@20000000 {
device_type = "memory";
compatible = "mmio-sram";
};
soc {
flash-controller@400c0000 {
compatible = "silabs,gecko-flash-controller";
label = "FLASH_CTRL";
reg = <0x400c0000 0x78>;
interrupts = <35 0>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@0 {
compatible = "soc-nv-flash";
label = "FLASH_0";
write-block-size = <4>;
};
};
usart0: usart@4000c000 { /* USART0 */
compatible = "silabs,gecko-usart";
reg = <0x4000c000 0x400>;

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@ -8,11 +8,15 @@
#include <silabs/efm32wg.dtsi>
/ {
flash@0 {
reg = <0 DT_SIZE_K(256)>;
};
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(32)>;
};
soc {
flash-controller@400c0000 {
flash0: flash@0 {
reg = <0 DT_SIZE_K(256)>;
};
};
};
};

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@ -12,17 +12,28 @@
};
};
flash0: flash@0 {
compatible = "soc-nv-flash";
label = "FLASH_0";
};
sram0: memory@20000000 {
device_type = "memory";
compatible = "mmio-sram";
};
soc {
flash-controller@400e0000 {
compatible = "silabs,gecko-flash-controller";
label = "FLASH_CTRL";
reg = <0x400e0000 0x78>;
interrupts = <24 0>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@0 {
compatible = "soc-nv-flash";
label = "FLASH_0";
write-block-size = <4>;
};
};
usart0: usart@40010000 { /* USART0 */
compatible = "silabs,gecko-usart";
reg = <0x40010000 0x400>;

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@ -8,11 +8,15 @@
#include <silabs/efr32fg1p.dtsi>
/ {
flash@0 {
reg = <0 DT_SIZE_K(256)>;
};
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(32)>;
};
soc {
flash-controller@400e0000 {
flash0: flash@0 {
reg = <0 DT_SIZE_K(256)>;
};
};
};
};

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@ -13,17 +13,28 @@
};
};
flash0: flash@0 {
compatible = "soc-nv-flash";
label = "FLASH_0";
};
sram0: memory@20000000 {
device_type = "memory";
compatible = "mmio-sram";
};
soc {
flash-controller@400e0000 {
compatible = "silabs,gecko-flash-controller";
label = "FLASH_CTRL";
reg = <0x400e0000 0x104>;
interrupts = <25 0>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@0 {
compatible = "soc-nv-flash";
label = "FLASH_0";
write-block-size = <4>;
};
};
usart0: usart@40010000 { /* USART0 */
compatible = "silabs,gecko-usart";
reg = <0x40010000 0x400>;

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@ -8,11 +8,15 @@
#include <silabs/efr32mg.dtsi>
/ {
flash@0 {
reg = <0 DT_SIZE_K(1024)>;
};
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(256)>;
};
soc {
flash-controller@400e0000 {
flash0: flash@0 {
reg = <0 DT_SIZE_K(1024)>;
};
};
};
};

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@ -0,0 +1,20 @@
#
# Copyright (c) 2018, Piotr Mienkowski
#
# SPDX-License-Identifier: Apache-2.0
#
---
title: Silicon Labs Gecko Flash Controller
version: 0.1
description: >
This binding gives a base representation of the Silicon Labs Gecko Flash Controller
inherits:
!include flash-controller.yaml
properties:
compatible:
constraint: "silabs,gecko-flash-controller"
...

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@ -29,6 +29,7 @@ zephyr_sources_ifdef(CONFIG_GPIO_GECKO emlib/src/em_gpio.c)
zephyr_sources_ifdef(CONFIG_UART_GECKO emlib/src/em_usart.c)
zephyr_sources_ifdef(CONFIG_LEUART_GECKO emlib/src/em_leuart.c)
zephyr_sources_ifdef(CONFIG_I2C_GECKO emlib/src/em_i2c.c)
zephyr_sources_ifdef(CONFIG_SOC_FLASH_GECKO emlib/src/em_msc.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_EFM32WG Device/SiliconLabs/EFM32WG/Source/system_efm32wg.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_EFR32FG1P Device/SiliconLabs/EFR32FG1P/Source/system_efr32fg1p.c)
zephyr_sources_ifdef(CONFIG_SOC_SERIES_EFM32HG Device/SiliconLabs/EFM32HG/Source/system_efm32hg.c)

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@ -29,4 +29,11 @@ config UART_GECKO
endif # SERIAL
if FLASH
config SOC_FLASH_GECKO
def_bool y
endif # FLASH
endif # SOC_EFM32HG

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@ -8,6 +8,9 @@
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define FLASH_DEV_BASE_ADDRESS SILABS_GECKO_FLASH_CONTROLLER_400C0000_BASE_ADDRESS
#define FLASH_DEV_NAME SILABS_GECKO_FLASH_CONTROLLER_400C0000_LABEL
#define CONFIG_USART_GECKO_0_BASE_ADDRESS SILABS_GECKO_USART_4000C000_BASE_ADDRESS
#define CONFIG_USART_GECKO_0_CURRENT_SPEED SILABS_GECKO_USART_4000C000_CURRENT_SPEED
#define CONFIG_USART_GECKO_0_IRQ_RX SILABS_GECKO_USART_4000C000_IRQ_0

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@ -29,4 +29,11 @@ config UART_GECKO
endif # SERIAL
if FLASH
config SOC_FLASH_GECKO
def_bool y
endif # FLASH
endif # SOC_EFM32

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@ -8,6 +8,9 @@
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define FLASH_DEV_BASE_ADDRESS SILABS_GECKO_FLASH_CONTROLLER_400C0000_BASE_ADDRESS
#define FLASH_DEV_NAME SILABS_GECKO_FLASH_CONTROLLER_400C0000_LABEL
#define CONFIG_USART_GECKO_0_BASE_ADDRESS SILABS_GECKO_USART_4000C000_BASE_ADDRESS
#define CONFIG_USART_GECKO_0_CURRENT_SPEED SILABS_GECKO_USART_4000C000_CURRENT_SPEED
#define CONFIG_USART_GECKO_0_IRQ_RX SILABS_GECKO_USART_4000C000_IRQ_0

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@ -29,4 +29,11 @@ config UART_GECKO
endif # SERIAL
if FLASH
config SOC_FLASH_GECKO
def_bool y
endif # FLASH
endif # SOC_EFR32FG1P

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@ -8,6 +8,9 @@
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define FLASH_DEV_BASE_ADDRESS SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS
#define FLASH_DEV_NAME SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL
#define CONFIG_USART_GECKO_0_BASE_ADDRESS SILABS_GECKO_USART_40010000_BASE_ADDRESS
#define CONFIG_USART_GECKO_0_CURRENT_SPEED SILABS_GECKO_USART_40010000_CURRENT_SPEED
#define CONFIG_USART_GECKO_0_IRQ_RX SILABS_GECKO_USART_40010000_IRQ_0

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@ -39,4 +39,11 @@ config I2C_GECKO
endif # I2C
if FLASH
config SOC_FLASH_GECKO
def_bool y
endif # FLASH
endif # SOC_EFR32MG12P

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@ -8,6 +8,9 @@
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define FLASH_DEV_BASE_ADDRESS SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS
#define FLASH_DEV_NAME SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL
#define CONFIG_USART_GECKO_0_BASE_ADDRESS SILABS_GECKO_USART_40010000_BASE_ADDRESS
#define CONFIG_USART_GECKO_0_CURRENT_SPEED SILABS_GECKO_USART_40010000_CURRENT_SPEED
#define CONFIG_USART_GECKO_0_IRQ_RX SILABS_GECKO_USART_40010000_IRQ_0