arch: arm: common Armv8-M support
This PR includes the required changes in order to support conditional compilation for Armv8-M architecture. Two variants of the Armv8-M architecture are defined: - the Armv8-M Baseline (backwards compatible with ARMv6-M), - the Armv8-M Mainline (backwards compatible with ARMv7-M). Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit is contained in:
parent
edbce1c14c
commit
a0a03d7597
21 changed files with 197 additions and 115 deletions
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@ -65,16 +65,26 @@ config CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP
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This option signifies the Cortex-M0 has some mechanisms that can map
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the vector table to SRAM
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config ARMV6_M
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config ARMV6_M_ARMV8_M_BASELINE
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bool
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# Omit prompt to signify "hidden" option
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default n
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select ATOMIC_OPERATIONS_C
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select ISA_THUMB2
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help
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This option signifies the use of an ARMv6-M processor implementation.
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This option signifies the use of an ARMv6-M processor
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implementation, or the use of an ARMv8-M processor
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supporting the Baseline implementation.
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config ARMV7_M
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Notes:
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- A Processing Element (PE) without the Main Extension
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is also referred to as a Baseline Implementation. A
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Baseline implementation has a subset of the instructions,
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registers, and features, of a Mainline implementation.
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- ARMv6-M compatibility is provided by all ARMv8-M
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implementations.
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config ARMV7_M_ARMV8_M_MAINLINE
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bool
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# Omit prompt to signify "hidden" option
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default n
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@ -84,40 +94,51 @@ config ARMV7_M
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select CPU_CORTEX_M_HAS_VTOR
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select CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
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help
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This option signifies the use of an ARMv7-M processor implementation.
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This option signifies the use of an ARMv7-M processor
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implementation, or the use of an ARMv8-M processor
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implementation supporting the Main Extension.
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Notes:
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- A Processing Element (PE) with the Main Extension is also
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referred to as a Mainline Implementation.
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- ARMv7-M compatibility requires the Main Extension.
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From https://developer.arm.com/products/architecture/m-profile:
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The Main Extension provides backwards compatibility
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with ARMv7-M.
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config CPU_CORTEX_M0
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bool
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# Omit prompt to signify "hidden" option
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select ARMV6_M
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select ARMV6_M_ARMV8_M_BASELINE
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help
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This option signifies the use of a Cortex-M0 CPU
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config CPU_CORTEX_M0PLUS
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bool
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# Omit prompt to signify "hidden" option
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select ARMV6_M
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select ARMV6_M_ARMV8_M_BASELINE
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help
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This option signifies the use of a Cortex-M0+ CPU
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config CPU_CORTEX_M3
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bool
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# Omit prompt to signify "hidden" option
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select ARMV7_M
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select ARMV7_M_ARMV8_M_MAINLINE
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help
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This option signifies the use of a Cortex-M3 CPU
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config CPU_CORTEX_M4
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bool
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# Omit prompt to signify "hidden" option
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select ARMV7_M
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select ARMV7_M_ARMV8_M_MAINLINE
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help
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This option signifies the use of a Cortex-M4 CPU
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config CPU_CORTEX_M7
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bool
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# Omit prompt to signify "hidden" option
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select ARMV7_M
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select ARMV7_M_ARMV8_M_MAINLINE
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default n
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help
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This option signifies the use of a Cortex-M7 CPU
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@ -177,7 +198,7 @@ config XIP
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endmenu
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menu "ARM Cortex-M0/M0+/M3/M4/M7 options"
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depends on ARMV6_M || ARMV7_M
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depends on ARMV6_M_ARMV8_M_BASELINE || ARMV7_M_ARMV8_M_MAINLINE
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config GEN_ISR_TABLES
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default y
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@ -58,14 +58,14 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__reset)
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SECTION_SUBSEC_FUNC(TEXT,_reset_section,__start)
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/* lock interrupts: will get unlocked when switch to main task */
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#if defined(CONFIG_ARMV6_M)
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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cpsid i
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#elif defined(CONFIG_ARMV7_M)
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
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msr BASEPRI, r0
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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#ifdef CONFIG_WDOG_INIT
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/* board-specific watchdog initialization is necessary */
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@ -39,7 +39,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
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.word __nmi
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.word __hard_fault
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#if defined(CONFIG_ARMV6_M)
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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.word __reserved
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.word __reserved
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.word __reserved
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@ -49,7 +49,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
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.word __reserved
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.word __svc
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.word __reserved
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#elif defined(CONFIG_ARMV7_M)
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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.word __mpu_fault
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.word __bus_fault
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.word __usage_fault
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@ -61,7 +61,7 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
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.word __debug_monitor
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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.word __reserved
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.word __pendsv
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#if defined(CONFIG_CORTEX_M_SYSTICK)
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@ -38,9 +38,9 @@ GTEXT(_vector_table)
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GTEXT(__reset)
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GTEXT(__nmi)
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GTEXT(__hard_fault)
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#if defined(CONFIG_ARMV6_M)
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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GTEXT(__svc)
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#elif defined(CONFIG_ARMV7_M)
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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GTEXT(__mpu_fault)
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GTEXT(__bus_fault)
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GTEXT(__usage_fault)
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@ -48,7 +48,7 @@ GTEXT(__svc)
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GTEXT(__debug_monitor)
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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GTEXT(__pendsv)
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GTEXT(__reserved)
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@ -120,15 +120,15 @@ SECTION_FUNC(TEXT, k_cpu_idle)
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mov lr, r0
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#endif
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#if defined(CONFIG_ARMV6_M)
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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cpsie i
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#elif defined(CONFIG_ARMV7_M)
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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/* clear BASEPRI so wfi is awakened by incoming interrupts */
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eors.n r0, r0
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msr BASEPRI, r0
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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wfi
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@ -177,7 +177,7 @@ SECTION_FUNC(TEXT, k_cpu_atomic_idle)
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/* r0: interrupt mask from caller */
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#if defined(CONFIG_ARMV6_M)
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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/* No BASEPRI, call wfe directly (SEVONPEND set in _CpuIdleInit()) */
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wfe
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@ -186,7 +186,7 @@ SECTION_FUNC(TEXT, k_cpu_atomic_idle)
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cpsie i
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_irq_disabled:
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#elif defined(CONFIG_ARMV7_M)
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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/* r1: zero, for setting BASEPRI (needs a register) */
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eors.n r1, r1
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@ -199,5 +199,5 @@ _irq_disabled:
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cpsie i
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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bx lr
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@ -90,12 +90,12 @@ SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, _ExcExit)
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#ifdef CONFIG_TIMESLICING
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push {lr}
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bl _update_time_slice_before_swap
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#if defined(CONFIG_ARMV6_M)
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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pop {r0}
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mov lr, r0
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#else
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pop {lr}
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#endif /* CONFIG_ARMV6_M */
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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#endif /* CONFIG_TIMESLICING */
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/* context switch required, pend the PendSV exception */
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@ -111,12 +111,12 @@ _EXIT_EXC:
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#ifdef CONFIG_STACK_SENTINEL
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push {lr}
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bl _check_stack_sentinel
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#if defined(CONFIG_ARMV6_M)
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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pop {r0}
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mov lr, r0
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#else
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pop {lr}
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#endif /* CONFIG_ARMV6_M */
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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#endif /* CONFIG_STACK_SENTINEL */
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bx lr
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@ -59,8 +59,8 @@ void _FaultDump(const NANO_ESF *esf, int fault)
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k_current_get(),
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esf->pc);
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_ARMV7_M)
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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int escalation = 0;
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if (3 == fault) { /* hard fault */
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@ -92,7 +92,7 @@ void _FaultDump(const NANO_ESF *esf, int fault)
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SCB->CFSR |= SCB_CFSR_USGFAULTSR_Msk;
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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}
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#endif
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@ -112,8 +112,9 @@ static void _FaultThreadShow(const NANO_ESF *esf)
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k_current_get(), esf->pc);
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}
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_ARMV7_M)
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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/* HardFault is used for all fault conditions on ARMv6-M. */
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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/**
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*
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@ -240,7 +241,7 @@ static void _DebugMonitor(const NANO_ESF *esf)
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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/**
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*
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@ -254,9 +255,9 @@ static void _HardFault(const NANO_ESF *esf)
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{
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PR_EXC("***** HARD FAULT *****\n");
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#if defined(CONFIG_ARMV6_M)
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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_FaultThreadShow(esf);
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#elif defined(CONFIG_ARMV7_M)
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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if (SCB->HFSR & SCB_HFSR_VECTTBL_Msk) {
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PR_EXC(" Bus fault on vector table read\n");
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} else if (SCB->HFSR & SCB_HFSR_FORCED_Msk) {
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@ -271,7 +272,7 @@ static void _HardFault(const NANO_ESF *esf)
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}
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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}
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/**
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@ -316,8 +317,9 @@ static void _FaultDump(const NANO_ESF *esf, int fault)
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case 3:
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_HardFault(esf);
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break;
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_ARMV7_M)
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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/* HardFault is used for all fault conditions on ARMv6-M. */
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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case 4:
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_MpuFault(esf, 0);
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break;
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@ -332,7 +334,7 @@ static void _FaultDump(const NANO_ESF *esf, int fault)
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break;
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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default:
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_ReservedException(esf, fault);
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break;
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@ -375,10 +377,10 @@ void _Fault(const NANO_ESF *esf)
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*/
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void _FaultInit(void)
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{
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_ARMV7_M)
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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}
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@ -20,15 +20,16 @@ _ASM_FILE_PROLOGUE
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GTEXT(_Fault)
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GTEXT(__hard_fault)
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_ARMV7_M)
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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/* HardFault is used for all fault conditions on ARMv6-M. */
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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GTEXT(__mpu_fault)
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GTEXT(__bus_fault)
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GTEXT(__usage_fault)
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GTEXT(__debug_monitor)
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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GTEXT(__reserved)
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/**
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@ -55,18 +56,19 @@ GTEXT(__reserved)
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*/
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SECTION_SUBSEC_FUNC(TEXT,__fault,__hard_fault)
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#if defined(CONFIG_ARMV6_M)
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#elif defined(CONFIG_ARMV7_M)
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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/* HardFault is used for all fault conditions on ARMv6-M. */
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__mpu_fault)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__bus_fault)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__usage_fault)
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SECTION_SUBSEC_FUNC(TEXT,__fault,__debug_monitor)
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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SECTION_SUBSEC_FUNC(TEXT,__fault,__reserved)
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#if defined(CONFIG_ARMV6_M)
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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/* force unlock interrupts */
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cpsie i
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@ -83,7 +85,7 @@ _stack_frame_msp:
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mrs r0, MSP
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_stack_frame_endif:
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#elif defined(CONFIG_ARMV7_M)
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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/* force unlock interrupts */
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eors.n r0, r0
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msr BASEPRI, r0
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@ -102,7 +104,7 @@ _stack_frame_endif:
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* frame is on the PSP */
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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push {lr}
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bl _Fault
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@ -146,12 +146,12 @@ void _irq_spurious(void *unused)
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#ifdef CONFIG_SYS_POWER_MANAGEMENT
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void _arch_isr_direct_pm(void)
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{
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#if defined(CONFIG_ARMV6_M)
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
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int key;
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/* irq_lock() does what we wan for this CPU */
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key = irq_lock();
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#elif defined(CONFIG_ARMV7_M)
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#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
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/* Lock all interrupts. irq_lock() will on this CPU only disable those
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* lower than BASEPRI, which is not what we want. See comments in
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* arch/arm/core/isr_wrapper.S
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@ -159,7 +159,7 @@ void _arch_isr_direct_pm(void)
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__asm__ volatile("cpsid i" : : : "memory");
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#else
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M */
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
|
||||
|
||||
if (_kernel.idle) {
|
||||
s32_t idle_val = _kernel.idle;
|
||||
|
@ -168,13 +168,13 @@ void _arch_isr_direct_pm(void)
|
|||
_sys_power_save_idle_exit(idle_val);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
|
||||
irq_unlock(key);
|
||||
#elif defined(CONFIG_ARMV7_M)
|
||||
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
|
||||
__asm__ volatile("cpsie i" : : : "memory");
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
|
||||
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -22,7 +22,7 @@ void _irq_do_offload(void)
|
|||
|
||||
void irq_offload(irq_offload_routine_t routine, void *parameter)
|
||||
{
|
||||
#if defined(CONFIG_ARMV6_M) && defined(CONFIG_ASSERT)
|
||||
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) && defined(CONFIG_ASSERT)
|
||||
/* Cortex M0 hardfaults if you make a SVC call with interrupts
|
||||
* locked.
|
||||
*/
|
||||
|
@ -30,7 +30,7 @@ void irq_offload(irq_offload_routine_t routine, void *parameter)
|
|||
|
||||
__asm__ volatile("mrs %0, PRIMASK;" : "=r" (key) : : "memory");
|
||||
__ASSERT(key == 0, "irq_offload called with interrupts locked\n");
|
||||
#endif
|
||||
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE && CONFIG_ASSERT */
|
||||
|
||||
k_sched_lock();
|
||||
offload_routine = routine;
|
||||
|
|
|
@ -72,7 +72,7 @@ SECTION_FUNC(TEXT, _isr_wrapper)
|
|||
ldr r0, [r2, #_kernel_offset_to_idle]
|
||||
cmp r0, #0
|
||||
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
|
||||
beq _idle_state_cleared
|
||||
movs.n r1, #0
|
||||
/* clear kernel idle state */
|
||||
|
@ -80,7 +80,7 @@ SECTION_FUNC(TEXT, _isr_wrapper)
|
|||
blx _sys_power_save_idle_exit
|
||||
_idle_state_cleared:
|
||||
|
||||
#elif defined(CONFIG_ARMV7_M)
|
||||
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
|
||||
ittt ne
|
||||
movne r1, #0
|
||||
/* clear kernel idle state */
|
||||
|
@ -88,22 +88,22 @@ _idle_state_cleared:
|
|||
blxne _sys_power_save_idle_exit
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
|
||||
|
||||
cpsie i /* re-enable interrupts (PRIMASK = 0) */
|
||||
#endif
|
||||
|
||||
mrs r0, IPSR /* get exception number */
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
|
||||
ldr r1, =16
|
||||
subs r0, r1 /* get IRQ number */
|
||||
lsls r0, #3 /* table is 8-byte wide */
|
||||
#elif defined(CONFIG_ARMV7_M)
|
||||
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
|
||||
sub r0, r0, #16 /* get IRQ number */
|
||||
lsl r0, r0, #3 /* table is 8-byte wide */
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
|
||||
ldr r1, =_sw_isr_table
|
||||
add r1, r1, r0 /* table entry: ISRs must have their MSB set to stay
|
||||
* in thumb mode */
|
||||
|
@ -113,24 +113,24 @@ _idle_state_cleared:
|
|||
stm sp!,{r0-r3} /* Save r0 to r4 into stack */
|
||||
push {lr}
|
||||
bl read_timer_end_of_isr
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
|
||||
pop {r3}
|
||||
mov lr,r3
|
||||
#else
|
||||
pop {lr}
|
||||
#endif
|
||||
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
|
||||
ldm sp!,{r0-r3} /* Restore r0 to r4 regs */
|
||||
#endif
|
||||
blx r3 /* call ISR */
|
||||
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
|
||||
pop {r3}
|
||||
mov lr, r3
|
||||
#elif defined(CONFIG_ARMV7_M)
|
||||
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
|
||||
pop {lr}
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
|
||||
|
||||
/* exception return is done in _IntExit() */
|
||||
b _IntExit
|
||||
|
|
|
@ -46,12 +46,12 @@ SECTION_FUNC(TEXT, __pendsv)
|
|||
/* Register the context switch */
|
||||
push {lr}
|
||||
bl _sys_k_event_logger_context_switch
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
|
||||
pop {r0}
|
||||
mov lr, r0
|
||||
#else
|
||||
pop {lr}
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
|
||||
#endif /* CONFIG_KERNEL_EVENT_LOGGER_CONTEXT_SWITCH */
|
||||
|
||||
/* load _kernel into r1 and current k_thread into r2 */
|
||||
|
@ -65,7 +65,7 @@ SECTION_FUNC(TEXT, __pendsv)
|
|||
/* save callee-saved + psp in thread */
|
||||
mrs ip, PSP
|
||||
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
|
||||
/* Store current r4-r7 */
|
||||
stmea r0!, {r4-r7}
|
||||
/* copy r8-r12 into r3-r7 */
|
||||
|
@ -76,7 +76,7 @@ SECTION_FUNC(TEXT, __pendsv)
|
|||
mov r7, ip
|
||||
/* store r8-12 */
|
||||
stmea r0!, {r3-r7}
|
||||
#elif defined(CONFIG_ARMV7_M)
|
||||
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
|
||||
stmia r0, {v1-v8, ip}
|
||||
#ifdef CONFIG_FP_SHARING
|
||||
add r0, r2, #_thread_offset_to_preempt_float
|
||||
|
@ -84,7 +84,7 @@ SECTION_FUNC(TEXT, __pendsv)
|
|||
#endif /* CONFIG_FP_SHARING */
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
|
||||
|
||||
/*
|
||||
* Prepare to clear PendSV with interrupts unlocked, but
|
||||
|
@ -97,14 +97,14 @@ SECTION_FUNC(TEXT, __pendsv)
|
|||
ldr v3, =_SCS_ICSR_UNPENDSV
|
||||
|
||||
/* protect the kernel state while we play with the thread lists */
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
|
||||
cpsid i
|
||||
#elif defined(CONFIG_ARMV7_M)
|
||||
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
|
||||
movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
|
||||
msr BASEPRI, r0
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
|
||||
|
||||
/* _kernel is still in r1 */
|
||||
|
||||
|
@ -130,7 +130,7 @@ SECTION_FUNC(TEXT, __pendsv)
|
|||
movs.n r3, #0
|
||||
str r3, [r2, #_thread_offset_to_basepri]
|
||||
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
|
||||
/* BASEPRI not available, previous interrupt disable state
|
||||
* maps to PRIMASK.
|
||||
*
|
||||
|
@ -158,7 +158,7 @@ _thread_irq_disabled:
|
|||
/* restore r4-r7, go back 9*4 bytes to the start of the stored block */
|
||||
subs r0, #36
|
||||
ldmia r0!, {r4-r7}
|
||||
#elif defined(CONFIG_ARMV7_M)
|
||||
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
|
||||
/* restore BASEPRI for the incoming thread */
|
||||
msr BASEPRI, r0
|
||||
|
||||
|
@ -188,7 +188,7 @@ _thread_irq_disabled:
|
|||
ldmia r0, {v1-v8, ip}
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
|
||||
|
||||
msr PSP, ip
|
||||
|
||||
|
@ -197,19 +197,19 @@ _thread_irq_disabled:
|
|||
push {lr}
|
||||
bl read_timer_end_of_swap
|
||||
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
|
||||
pop {r3}
|
||||
mov lr,r3
|
||||
#else
|
||||
pop {lr}
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
|
||||
ldm sp!,{r0-r3} /* Load back regs ro to r4 */
|
||||
#endif /* CONFIG_EXECUTION_BENCHMARKING */
|
||||
|
||||
/* exc return */
|
||||
bx lr
|
||||
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
|
||||
SECTION_FUNC(TEXT, __svc)
|
||||
/* Use EXC_RETURN state to find out if stack frame is on the
|
||||
* MSP or PSP
|
||||
|
@ -256,7 +256,7 @@ _oops:
|
|||
blx _do_kernel_oops
|
||||
pop {pc}
|
||||
|
||||
#elif defined(CONFIG_ARMV7_M)
|
||||
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
|
||||
/**
|
||||
*
|
||||
* @brief Service call handler
|
||||
|
@ -326,7 +326,7 @@ _oops:
|
|||
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
|
||||
|
||||
/**
|
||||
*
|
||||
|
@ -370,12 +370,12 @@ SECTION_FUNC(TEXT, __swap)
|
|||
#ifdef CONFIG_EXECUTION_BENCHMARKING
|
||||
push {lr}
|
||||
bl read_timer_start_of_swap
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
|
||||
pop {r3}
|
||||
mov lr,r3
|
||||
#else
|
||||
pop {lr}
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
|
||||
#endif /* CONFIG_EXECUTION_BENCHMARKING */
|
||||
ldr r1, =_kernel
|
||||
ldr r2, [r1, #_kernel_offset_to_current]
|
||||
|
@ -389,7 +389,7 @@ SECTION_FUNC(TEXT, __swap)
|
|||
ldr r1, [r1]
|
||||
str r1, [r2, #_thread_offset_to_swap_return_value]
|
||||
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
|
||||
/* No priority-based interrupt masking on M0/M0+,
|
||||
* pending PendSV is used instead of svc
|
||||
*/
|
||||
|
@ -403,11 +403,11 @@ SECTION_FUNC(TEXT, __swap)
|
|||
* of a higher priority pending.
|
||||
*/
|
||||
cpsie i
|
||||
#elif defined(CONFIG_ARMV7_M)
|
||||
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
|
||||
svc #0
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
|
||||
|
||||
/* coming back from exception, r2 still holds the pointer to _current */
|
||||
ldr r0, [r2, #_thread_offset_to_swap_return_value]
|
||||
|
|
|
@ -55,12 +55,12 @@ static ALWAYS_INLINE int _IsInIsr(void)
|
|||
/* Only non-NULL if currently running an offloaded function */
|
||||
|| offload_routine != NULL
|
||||
#endif
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
|
||||
/* On ARMv6-M there is no nested execution bit, so we check
|
||||
* exception 3, hard fault, to a detect a nested exception.
|
||||
*/
|
||||
|| (vector == 3)
|
||||
#elif defined(CONFIG_ARMV7_M)
|
||||
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
|
||||
/* If not in thread mode, and if RETTOBASE bit in ICSR is 0,
|
||||
* then there are preempted active exceptions to execute.
|
||||
*/
|
||||
|
@ -75,7 +75,7 @@ static ALWAYS_INLINE int _IsInIsr(void)
|
|||
#endif /* CONFIG_BOARD_QEMU_CORTEX_M3 */
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
|
||||
;
|
||||
}
|
||||
|
||||
|
@ -119,8 +119,8 @@ static ALWAYS_INLINE void _ExcSetup(void)
|
|||
*/
|
||||
static ALWAYS_INLINE void _ClearFaults(void)
|
||||
{
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
#elif defined(CONFIG_ARMV7_M)
|
||||
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
|
||||
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
|
||||
/* Reset all faults */
|
||||
SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
|
||||
SCB_CFSR_MEMFAULTSR_Msk |
|
||||
|
@ -130,7 +130,7 @@ static ALWAYS_INLINE void _ClearFaults(void)
|
|||
SCB->HFSR = 0xffffffff;
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
|
||||
}
|
||||
|
||||
#endif /* _ASMLANGUAGE */
|
||||
|
|
|
@ -59,14 +59,14 @@ _arch_switch_to_main_thread(struct k_thread *main_thread,
|
|||
"msr PSP, %0 \t\n"
|
||||
|
||||
/* unlock interrupts */
|
||||
#ifdef CONFIG_ARMV6_M
|
||||
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
|
||||
"cpsie i \t\n"
|
||||
#elif defined(CONFIG_ARMV7_M)
|
||||
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
|
||||
"movs %%r1, #0 \n\t"
|
||||
"msr BASEPRI, %%r1 \n\t"
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
|
||||
|
||||
/* branch to _thread_entry(_main, 0, 0, 0) */
|
||||
"mov %%r0, %1 \n\t"
|
||||
|
|
25
dts/arm/armv8-m.dtsi
Normal file
25
dts/arm/armv8-m.dtsi
Normal file
|
@ -0,0 +1,25 @@
|
|||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&nvic>;
|
||||
ranges;
|
||||
|
||||
nvic: interrupt-controller@e000e100 {
|
||||
compatible = "arm,v8m-nvic";
|
||||
reg = <0xe000e100 0xc00>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
systick: timer@e000e010 {
|
||||
compatible = "arm,armv8m-systick";
|
||||
reg = <0xe000e010 0x10>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
32
dts/bindings/interrupt-controller/arm,v8m-nvic.yaml
Normal file
32
dts/bindings/interrupt-controller/arm,v8m-nvic.yaml
Normal file
|
@ -0,0 +1,32 @@
|
|||
---
|
||||
title: ARMv8-M NVIC Interrupt Controller
|
||||
version: 0.1
|
||||
|
||||
description: >
|
||||
This binding describes the ARMv8-M Nested Vectored Interrupt Controller.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
category: required
|
||||
type: string
|
||||
description: compatible strings
|
||||
constraint: "arm,v8m-nvic"
|
||||
|
||||
reg:
|
||||
category: required
|
||||
type: int
|
||||
description: mmio register space
|
||||
generation: define
|
||||
|
||||
arm,num-irq-priority-bits:
|
||||
category: required
|
||||
type: int
|
||||
description: number of bits of IRQ priorities
|
||||
generation: define
|
||||
|
||||
cell_string: IRQ
|
||||
|
||||
"#cells":
|
||||
- irq
|
||||
- priority
|
||||
...
|
|
@ -118,13 +118,13 @@ static ALWAYS_INLINE unsigned int _arch_irq_lock(void)
|
|||
{
|
||||
unsigned int key;
|
||||
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
|
||||
__asm__ volatile("mrs %0, PRIMASK;"
|
||||
"cpsid i"
|
||||
: "=r" (key)
|
||||
:
|
||||
: "memory");
|
||||
#elif defined(CONFIG_ARMV7_M)
|
||||
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
|
||||
unsigned int tmp;
|
||||
|
||||
__asm__ volatile(
|
||||
|
@ -136,7 +136,7 @@ static ALWAYS_INLINE unsigned int _arch_irq_lock(void)
|
|||
: "memory");
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
|
||||
|
||||
return key;
|
||||
}
|
||||
|
@ -163,16 +163,16 @@ static ALWAYS_INLINE unsigned int _arch_irq_lock(void)
|
|||
|
||||
static ALWAYS_INLINE void _arch_irq_unlock(unsigned int key)
|
||||
{
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
|
||||
if (key) {
|
||||
return;
|
||||
}
|
||||
__asm__ volatile("cpsie i" : : : "memory");
|
||||
#elif defined(CONFIG_ARMV7_M)
|
||||
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
|
||||
__asm__ volatile("msr BASEPRI, %0" : : "r"(key) : "memory");
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
|
||||
}
|
||||
|
||||
|
||||
|
|
|
@ -94,11 +94,11 @@ typedef enum {
|
|||
Reset_IRQn = -15,
|
||||
NonMaskableInt_IRQn = -14,
|
||||
HardFault_IRQn = -13,
|
||||
#if defined(CONFIG_ARMV7_M)
|
||||
#if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
|
||||
MemoryManagement_IRQn = -12,
|
||||
BusFault_IRQn = -11,
|
||||
UsageFault_IRQn = -10,
|
||||
#endif /* CONFIG_ARMV7_M */
|
||||
#endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
|
||||
SVCall_IRQn = -5,
|
||||
DebugMonitor_IRQn = -4,
|
||||
PendSV_IRQn = -2,
|
||||
|
|
|
@ -34,7 +34,7 @@ extern void _SysFatalErrorHandler(unsigned int reason, const NANO_ESF *esf);
|
|||
#define _SVC_CALL_IRQ_OFFLOAD 1
|
||||
#define _SVC_CALL_RUNTIME_EXCEPT 2
|
||||
|
||||
#if defined(CONFIG_ARMV6_M)
|
||||
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
|
||||
/* ARMv6 will hard-fault if SVC is called with interrupts locked. Just
|
||||
* force them unlocked, the thread is in an undefined state anyway
|
||||
*
|
||||
|
@ -53,7 +53,7 @@ extern void _SysFatalErrorHandler(unsigned int reason, const NANO_ESF *esf);
|
|||
: "memory"); \
|
||||
CODE_UNREACHABLE; \
|
||||
} while (0)
|
||||
#elif defined(CONFIG_ARMV7_M)
|
||||
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
|
||||
#define _ARCH_EXCEPT(reason_p) do { \
|
||||
__asm__ volatile ( \
|
||||
"eors.n r0, r0\n\t" \
|
||||
|
@ -67,7 +67,7 @@ extern void _SysFatalErrorHandler(unsigned int reason, const NANO_ESF *esf);
|
|||
} while (0)
|
||||
#else
|
||||
#error Unknown ARM architecture
|
||||
#endif /* CONFIG_ARMV6_M */
|
||||
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
@ -1,4 +1,4 @@
|
|||
tests:
|
||||
test:
|
||||
filter: CONFIG_ARMV7_M
|
||||
filter: CONFIG_ARMV7_M_ARMV8_M_MAINLINE
|
||||
tags: core bat_commit
|
||||
|
|
|
@ -1,4 +1,4 @@
|
|||
tests:
|
||||
test:
|
||||
filter: CONFIG_GEN_ISR_TABLES and CONFIG_ARMV7_M
|
||||
filter: CONFIG_GEN_ISR_TABLES and CONFIG_ARMV7_M_ARMV8_M_MAINLINE
|
||||
tags: core
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue