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gpio: ti cc32xx: Add device tree support for GPIO

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Convert gpio_cc32xx driver over to using device tree. Added binding
files, updates to dts for various SoCs that use cc32xx.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2018-11-01 03:55:34 -05:00 • committed by Kumar Gala
commit ac7da0b65c
5 changed files with 121 additions and 78 deletions
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53
drivers/gpio/Kconfig.cc32xx
View file

@ -4,6 +4,7 @@
menuconfig GPIO_CC32XX
bool "TI CC32XX GPIO driver"
depends on GPIO && SOC_FAMILY_TISIMPLELINK
select HAS_DTS_GPIO
help
Enable the GPIO driver on TI SimpleLink CC32xx boards
@ -15,74 +16,22 @@ config GPIO_CC32XX_A0
help
Include support for the GPIO port A0.
config GPIO_CC32XX_A0_NAME
string "Driver name"
depends on GPIO_CC32XX_A0
default "GPIO_A0"
config GPIO_CC32XX_A0_IRQ_PRI
int "GPIO A0 interrupt priority"
depends on GPIO_CC32XX_A0
range 0 5
default 1
help
CC32XX GPIO A0 IRQ priority.
config GPIO_CC32XX_A1
bool "GPIO block A1"
depends on GPIO_CC32XX
help
Include support for the GPIO port A1.
config GPIO_CC32XX_A1_NAME
string "Driver name"
depends on GPIO_CC32XX_A1
default "GPIO_A1"
config GPIO_CC32XX_A1_IRQ_PRI
int "GPIO A1 interrupt priority"
depends on GPIO_CC32XX_A1
range 0 5
default 1
help
CC32XX GPIO A1 IRQ priority.
config GPIO_CC32XX_A2
bool "GPIO block A2"
depends on GPIO_CC32XX
help
Include support for the GPIO port A2.
config GPIO_CC32XX_A2_NAME
string "Driver name"
depends on GPIO_CC32XX_A2
default "GPIO_A2"
config GPIO_CC32XX_A2_IRQ_PRI
int "GPIO A2 interrupt priority"
depends on GPIO_CC32XX_A2
range 0 5
default 1
help
CC32XX GPIO A2 IRQ priority.
config GPIO_CC32XX_A3
bool "GPIO block A3"
depends on GPIO_CC32XX
help
Include support for the GPIO port A3.
config GPIO_CC32XX_A3_NAME
string "Driver name"
depends on GPIO_CC32XX_A3
default "GPIO_A3"
config GPIO_CC32XX_A3_IRQ_PRI
int "GPIO A3 interrupt priority"
depends on GPIO_CC32XX_A3
range 0 5
default 1
help
CC32XX GPIO A3 IRQ priority.
endif # GPIO_CC32XX

46
drivers/gpio/gpio_cc32xx.c
View file

@ -25,12 +25,6 @@
#include "gpio_utils.h"
/* Note: Zephyr uses exception numbers, vs the IRQ #s used by the CC32XX SDK */
#define EXCEPTION_GPIOA0 0 /* (INT_GPIOA0 - 16) = (16-16) */
#define EXCEPTION_GPIOA1 1 /* (INT_GPIOA1 - 16) = (17-16) */
#define EXCEPTION_GPIOA2 2 /* (INT_GPIOA2 - 16) = (18-16) */
#define EXCEPTION_GPIOA3 3 /* (INT_GPIOA3 - 16) = (19-16) */
struct gpio_cc32xx_config {
/* base address of GPIO port */
unsigned long port_base;
@ -206,8 +200,8 @@ static const struct gpio_driver_api api_funcs = {
#ifdef CONFIG_GPIO_CC32XX_A0
static const struct gpio_cc32xx_config gpio_cc32xx_a0_config = {
.port_base = GPIOA0_BASE,
.irq_num = INT_GPIOA0,
.port_base = CONFIG_GPIO_CC32XX_A0_BASE_ADDRESS,
.irq_num = CONFIG_GPIO_CC32XX_A0_IRQ+16,
};
static struct device DEVICE_NAME_GET(gpio_cc32xx_a0);
@ -217,11 +211,11 @@ static int gpio_cc32xx_a0_init(struct device *dev)
{
ARG_UNUSED(dev);
IRQ_CONNECT(EXCEPTION_GPIOA0, CONFIG_GPIO_CC32XX_A0_IRQ_PRI,
IRQ_CONNECT(CONFIG_GPIO_CC32XX_A0_IRQ, CONFIG_GPIO_CC32XX_A0_IRQ_PRI,
gpio_cc32xx_port_isr, DEVICE_GET(gpio_cc32xx_a0), 0);
MAP_IntPendClear(INT_GPIOA0);
irq_enable(EXCEPTION_GPIOA0);
MAP_IntPendClear(CONFIG_GPIO_CC32XX_A0_IRQ+16);
irq_enable(CONFIG_GPIO_CC32XX_A0_IRQ);
return 0;
}
@ -236,8 +230,8 @@ DEVICE_AND_API_INIT(gpio_cc32xx_a0, CONFIG_GPIO_CC32XX_A0_NAME,
#ifdef CONFIG_GPIO_CC32XX_A1
static const struct gpio_cc32xx_config gpio_cc32xx_a1_config = {
.port_base = GPIOA1_BASE,
.irq_num = INT_GPIOA1,
.port_base = CONFIG_GPIO_CC32XX_A1_BASE_ADDRESS,
.irq_num = CONFIG_GPIO_CC32XX_A1_IRQ+16,
};
static struct device DEVICE_NAME_GET(gpio_cc32xx_a1);
@ -247,11 +241,11 @@ static int gpio_cc32xx_a1_init(struct device *dev)
{
ARG_UNUSED(dev);
IRQ_CONNECT(EXCEPTION_GPIOA1, CONFIG_GPIO_CC32XX_A1_IRQ_PRI,
IRQ_CONNECT(CONFIG_GPIO_CC32XX_A1_IRQ, CONFIG_GPIO_CC32XX_A1_IRQ_PRI,
gpio_cc32xx_port_isr, DEVICE_GET(gpio_cc32xx_a1), 0);
MAP_IntPendClear(INT_GPIOA1);
irq_enable(EXCEPTION_GPIOA1);
MAP_IntPendClear(CONFIG_GPIO_CC32XX_A1_IRQ+16);
irq_enable(CONFIG_GPIO_CC32XX_A1_IRQ);
return 0;
}
@ -266,8 +260,8 @@ DEVICE_AND_API_INIT(gpio_cc32xx_a1, CONFIG_GPIO_CC32XX_A1_NAME,
#ifdef CONFIG_GPIO_CC32XX_A2
static const struct gpio_cc32xx_config gpio_cc32xx_a2_config = {
.port_base = GPIOA2_BASE,
.irq_num = INT_GPIOA2,
.port_base = CONFIG_GPIO_CC32XX_A2_BASE_ADDRESS,
.irq_num = CONFIG_GPIO_CC32XX_A2_IRQ+16,
};
static struct device DEVICE_NAME_GET(gpio_cc32xx_a2);
@ -277,11 +271,11 @@ static int gpio_cc32xx_a2_init(struct device *dev)
{
ARG_UNUSED(dev);
IRQ_CONNECT(EXCEPTION_GPIOA2, CONFIG_GPIO_CC32XX_A2_IRQ_PRI,
IRQ_CONNECT(CONFIG_GPIO_CC32XX_A2_IRQ, CONFIG_GPIO_CC32XX_A2_IRQ_PRI,
gpio_cc32xx_port_isr, DEVICE_GET(gpio_cc32xx_a2), 0);
MAP_IntPendClear(INT_GPIOA2);
irq_enable(EXCEPTION_GPIOA2);
MAP_IntPendClear(CONFIG_GPIO_CC32XX_A2_IRQ+16);
irq_enable(CONFIG_GPIO_CC32XX_A2_IRQ);
return 0;
}
@ -296,8 +290,8 @@ DEVICE_AND_API_INIT(gpio_cc32xx_a2, CONFIG_GPIO_CC32XX_A2_NAME,
#ifdef CONFIG_GPIO_CC32XX_A3
static const struct gpio_cc32xx_config gpio_cc32xx_a3_config = {
.port_base = GPIOA3_BASE,
.irq_num = INT_GPIOA3,
.port_base = CONFIG_GPIO_CC32XX_A3_BASE_ADDRESS,
.irq_num = CONFIG_GPIO_CC32XX_A3_IRQ+16,
};
static struct device DEVICE_NAME_GET(gpio_cc32xx_a3);
@ -307,11 +301,11 @@ static int gpio_cc32xx_a3_init(struct device *dev)
{
ARG_UNUSED(dev);
IRQ_CONNECT(EXCEPTION_GPIOA3, CONFIG_GPIO_CC32XX_A3_IRQ_PRI,
IRQ_CONNECT(CONFIG_GPIO_CC32XX_A3_IRQ, CONFIG_GPIO_CC32XX_A3_IRQ_PRI,
gpio_cc32xx_port_isr, DEVICE_GET(gpio_cc32xx_a3), 0);
MAP_IntPendClear(INT_GPIOA3);
irq_enable(EXCEPTION_GPIOA3);
MAP_IntPendClear(CONFIG_GPIO_CC32XX_A3_IRQ+16);
irq_enable(CONFIG_GPIO_CC32XX_A3_IRQ);
return 0;
}

40
dts/arm/ti/cc32xx.dtsi
View file

@ -1,6 +1,7 @@
#include <arm/armv7-m.dtsi>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>
#define INT_UARTA0 21 // UART0 Rx and Tx
#define INT_UARTA1 22 // UART1 Rx and Tx
@ -11,6 +12,10 @@
#define EXP_UARTA0 (INT_UARTA0 - 16)
#define EXP_UARTA1 (INT_UARTA1 - 16)
#define EXP_I2CA0 (INT_I2CA0 - 16)
#define EXC_GPIOA0 0 /* (INT_GPIOA0 - 16) = (16-16) */
#define EXC_GPIOA1 1 /* (INT_GPIOA1 - 16) = (17-16) */
#define EXC_GPIOA2 2 /* (INT_GPIOA2 - 16) = (18-16) */
#define EXC_GPIOA3 3 /* (INT_GPIOA3 - 16) = (19-16) */
/ {
cpus {
@ -61,6 +66,41 @@
label= "I2C_0";
};
gpioa0: gpio@40004000 {
compatible = "ti,cc32xx-gpio";
reg = <0x40004000 0x1000>;
interrupts = <0 1>;
label = "GPIO_A0";
gpio-controller;
#gpio-cells = <2>;
};
gpioa1: gpio@40005000 {
compatible = "ti,cc32xx-gpio";
reg = <0x40005000 0x1000>;
interrupts = <1 1>;
label = "GPIO_A1";
gpio-controller;
#gpio-cells = <2>;
};
gpioa2: gpio@40006000 {
compatible = "ti,cc32xx-gpio";
reg = <0x40006000 0x1000>;
interrupts = <2 1>;
label = "GPIO_A2";
gpio-controller;
#gpio-cells = <2>;
};
gpioa3: gpio@40007000 {
compatible = "ti,cc32xx-gpio";
reg = <0x40007000 0x1000>;
interrupts = <3 1>;
label = "GPIO_A3";
gpio-controller;
#gpio-cells = <2>;
};
};
};

40
dts/bindings/gpio/ti,cc32xx-gpio.yaml Normal file
View file

@ -0,0 +1,40 @@
---
# SPDX-License-Identifier: Apache-2.0
title: TI CC32XX GPIO
version: 0.1
description: >
This is a representation of the TI CC32XX GPIO node
properties:
compatible:
type: string
category: required
description: compatible strings
constraint: "ti,cc32xx-gpio"
generation: define
reg:
type: int
description: mmio register space
generation: define
category: required
interrupts:
type: compound
category: required
description: required interrupts
generation: define
label:
type: string
category: required
description: Human readable string describing the device (used by Zephyr for API name)
generation: define
cell_string: GPIO
"#cells":
- pin
- flags
...

20
soc/arm/ti_simplelink/cc32xx/dts_fixup.h
View file

@ -9,4 +9,24 @@
#define CONFIG_I2C_0_IRQ TI_CC32XX_I2C_40020000_IRQ_0
#define CONFIG_I2C_0_IRQ_PRIORITY TI_CC32XX_I2C_40020000_IRQ_0_PRIORITY
#define CONFIG_GPIO_CC32XX_A0_BASE_ADDRESS TI_CC32XX_GPIO_40004000_BASE_ADDRESS
#define CONFIG_GPIO_CC32XX_A0_IRQ TI_CC32XX_GPIO_40004000_IRQ_0
#define CONFIG_GPIO_CC32XX_A0_IRQ_PRI TI_CC32XX_GPIO_40004000_IRQ_0_PRIORITY
#define CONFIG_GPIO_CC32XX_A0_NAME TI_CC32XX_GPIO_40004000_LABEL
#define CONFIG_GPIO_CC32XX_A1_BASE_ADDRESS TI_CC32XX_GPIO_40005000_BASE_ADDRESS
#define CONFIG_GPIO_CC32XX_A1_IRQ TI_CC32XX_GPIO_40005000_IRQ_0
#define CONFIG_GPIO_CC32XX_A1_IRQ_PRI TI_CC32XX_GPIO_40005000_IRQ_0_PRIORITY
#define CONFIG_GPIO_CC32XX_A1_NAME TI_CC32XX_GPIO_40005000_LABEL
#define CONFIG_GPIO_CC32XX_A2_BASE_ADDRESS TI_CC32XX_GPIO_40006000_BASE_ADDRESS
#define CONFIG_GPIO_CC32XX_A2_IRQ TI_CC32XX_GPIO_40006000_IRQ_0
#define CONFIG_GPIO_CC32XX_A2_IRQ_PRI TI_CC32XX_GPIO_40006000_IRQ_0_PRIORITY
#define CONFIG_GPIO_CC32XX_A2_NAME TI_CC32XX_GPIO_40006000_LABEL
#define CONFIG_GPIO_CC32XX_A3_BASE_ADDRESS TI_CC32XX_GPIO_40007000_BASE_ADDRESS
#define CONFIG_GPIO_CC32XX_A3_IRQ TI_CC32XX_GPIO_40007000_IRQ_0
#define CONFIG_GPIO_CC32XX_A3_IRQ_PRI TI_CC32XX_GPIO_40007000_IRQ_0_PRIORITY
#define CONFIG_GPIO_CC32XX_A3_NAME TI_CC32XX_GPIO_40007000_LABEL
/* End of SoC Level DTS fixup file */