soc: st: add STM32L471xG
This commit adds support for STM32L471xG. Since STM32L475 only adds USB, stm32l475.dtsi now includes stm32l471.dtsi Signed-off-by: Kiril Zyapkov <k.zyapkov@allterco.com>
This commit is contained in:
Kiril Zyapkov
Kumar Gala
parent
6194b7676c
commit
23cb7dd660
5 changed files with 234 additions and 162 deletions
172
dts/arm/st/l4/stm32l471.dtsi
Normal file
172
dts/arm/st/l4/stm32l471.dtsi
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@ -0,0 +1,172 @@
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/*
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* Copyright (c) 2017 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/l4/stm32l4.dtsi>
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/ {
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soc {
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pinctrl: pin-controller@48000000 {
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gpiod: gpio@48000c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
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label = "GPIOD";
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};
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gpioe: gpio@48001000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48001000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
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label = "GPIOE";
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};
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gpiof: gpio@48001400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48001400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
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label = "GPIOF";
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};
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gpiog: gpio@48001800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48001800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
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label = "GPIOG";
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};
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};
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uart4: serial@40004c00 {
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compatible = "st,stm32-uart";
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reg = <0x40004c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
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interrupts = <52 0>;
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status = "disabled";
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label = "UART_4";
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};
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uart5: serial@40005000 {
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compatible = "st,stm32-uart";
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reg = <0x40005000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
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interrupts = <53 0>;
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status = "disabled";
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label = "UART_5";
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};
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i2c2: i2c@40005800 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
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interrupts = <33 0>, <34 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label= "I2C_2";
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};
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spi3: spi@40003c00 {
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compatible = "st,stm32-spi-fifo";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
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interrupts = <51 5>;
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status = "disabled";
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label = "SPI_3";
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};
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timers3: timers@40000400 {
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compatible = "st,stm32-timers";
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reg = <0x40000400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
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status = "disabled";
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label = "TIMERS_3";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <10000>;
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label = "PWM_3";
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#pwm-cells = <2>;
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};
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};
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timers4: timers@40000800 {
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compatible = "st,stm32-timers";
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reg = <0x40000800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
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status = "disabled";
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label = "TIMERS_4";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <10000>;
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label = "PWM_4";
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#pwm-cells = <2>;
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};
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};
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timers5: timers@40000c00 {
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compatible = "st,stm32-timers";
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reg = <0x40000c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
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status = "disabled";
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label = "TIMERS_5";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <0>;
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label = "PWM_5";
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#pwm-cells = <2>;
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};
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};
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timers8: timers@40013400 {
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compatible = "st,stm32-timers";
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reg = <0x40013400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
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status = "disabled";
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label = "TIMERS_8";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <10000>;
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label = "PWM_8";
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#pwm-cells = <2>;
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};
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};
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timers17: timers@40014800 {
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compatible = "st,stm32-timers";
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reg = <0x40014800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
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status = "disabled";
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label = "TIMERS_17";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <10000>;
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label = "PWM_17";
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#pwm-cells = <2>;
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};
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};
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};
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};
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21
dts/arm/st/l4/stm32l471Xg.dtsi
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21
dts/arm/st/l4/stm32l471Xg.dtsi
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@ -0,0 +1,21 @@
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/*
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* Copyright (c) 2018 Allterco Robotics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <st/l4/stm32l471.dtsi>
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/ {
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(128)>;
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};
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soc {
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flash-controller@40022000 {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_K(1024)>;
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};
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};
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};
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};
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@ -4,91 +4,10 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/l4/stm32l4.dtsi>
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#include <st/l4/stm32l471.dtsi>
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/ {
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soc {
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pinctrl: pin-controller@48000000 {
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gpiod: gpio@48000c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
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label = "GPIOD";
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};
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gpioe: gpio@48001000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48001000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
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label = "GPIOE";
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};
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gpiof: gpio@48001400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48001400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
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label = "GPIOF";
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};
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gpiog: gpio@48001800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48001800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
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label = "GPIOG";
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};
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};
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uart4: serial@40004c00 {
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compatible = "st,stm32-uart";
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reg = <0x40004c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
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interrupts = <52 0>;
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status = "disabled";
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label = "UART_4";
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};
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uart5: serial@40005000 {
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compatible = "st,stm32-uart";
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reg = <0x40005000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
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interrupts = <53 0>;
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status = "disabled";
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label = "UART_5";
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};
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i2c2: i2c@40005800 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
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interrupts = <33 0>, <34 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label= "I2C_2";
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};
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spi3: spi@40003c00 {
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compatible = "st,stm32-spi-fifo";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
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interrupts = <51 5>;
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status = "disabled";
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label = "SPI_3";
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};
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otgfs_phy: otgfs_phy {
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compatible = "usb-nop-xceiv";
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#phy-cells = <0>;
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@ -107,85 +26,5 @@
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status = "disabled";
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label= "OTGFS";
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};
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timers3: timers@40000400 {
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compatible = "st,stm32-timers";
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reg = <0x40000400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
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status = "disabled";
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label = "TIMERS_3";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <10000>;
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label = "PWM_3";
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#pwm-cells = <2>;
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};
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};
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timers4: timers@40000800 {
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compatible = "st,stm32-timers";
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reg = <0x40000800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
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status = "disabled";
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label = "TIMERS_4";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <10000>;
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label = "PWM_4";
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#pwm-cells = <2>;
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};
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};
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timers5: timers@40000c00 {
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compatible = "st,stm32-timers";
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reg = <0x40000c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
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status = "disabled";
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label = "TIMERS_5";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <0>;
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label = "PWM_5";
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#pwm-cells = <2>;
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};
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};
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timers8: timers@40013400 {
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compatible = "st,stm32-timers";
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reg = <0x40013400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
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status = "disabled";
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label = "TIMERS_8";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <10000>;
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label = "PWM_8";
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#pwm-cells = <2>;
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};
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};
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timers17: timers@40014800 {
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compatible = "st,stm32-timers";
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reg = <0x40014800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
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status = "disabled";
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label = "TIMERS_17";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <10000>;
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label = "PWM_17";
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#pwm-cells = <2>;
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};
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};
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};
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};
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37
soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l471xx
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37
soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l471xx
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@ -0,0 +1,37 @@
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# Kconfig - ST Microelectronics STM32L476RG MCU
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#
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# Copyright (c) 2018 Allterco Robotics
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_STM32L471XX
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config SOC
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string
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default "stm32l471xx"
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config NUM_IRQS
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int
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default 82
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if GPIO_STM32
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config GPIO_STM32_PORTD
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def_bool y
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config GPIO_STM32_PORTE
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default y
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config GPIO_STM32_PORTF
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default y
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config GPIO_STM32_PORTG
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default y
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config GPIO_STM32_PORTH
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default y
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endif # GPIO_STM32
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endif # SOC_STM32L471XX
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@ -28,4 +28,7 @@ config SOC_STM32L475XG
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config SOC_STM32L4R5XI
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bool "STM32L4R5XI"
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config SOC_STM32L471XX
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bool "STM32L471XX"
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endchoice
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