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dts: provide stm32 soc dtsi files for stm32 base boards

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This commit provides dtsi files for available stm32 base boards.
For now only uart nodes and IRQ number are provided in order to
enable delivery of coherent material.

It also clears additional content from stm32f103xb.dtsi

Change-Id: I62d932c7f22b56e95bcd9566ce39e14a393dd640
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Erwan Gouriou 2017-03-06 11:11:19 +01:00 • committed by Kumar Gala
commit d899ce16b0
12 changed files with 257 additions and 156 deletions
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12
dts/arm/nucleo_l476rg.dts
View file

@ -16,19 +16,9 @@
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
leds {
compatible = "gpio-leds";
green {
gpios = <&gpioa 5 0>;
};
};
};
&clk_hse {
clock-frequency = <8000000>;
};
&usart2 {
baud-rate = <115200>;
status = "ok";
};

15
dts/arm/olimexino_stm32.dts
View file

@ -16,22 +16,9 @@
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
leds {
compatible = "gpio-leds";
green {
gpios = <&gpioa 5 0>;
};
yellow {
gpios = <&gpioa 1 0>;
};
};
};
&clk_hse {
clock-frequency = <72000000>;
};
&usart1 {
baud-rate = <115200>;
status = "ok";
};

16
dts/arm/st/mem.h
View file

@ -4,10 +4,26 @@
#if defined(CONFIG_SOC_STM32F103XB)
#define DT_FLASH_SIZE 0x20000
#define DT_SRAM_SIZE 0x5000
#elif defined(CONFIG_SOC_STM32F103XE)
#define DT_FLASH_SIZE 0x80000
#define DT_SRAM_SIZE 0x10000
#elif defined(CONFIG_SOC_STM32F107XC)
#define DT_FLASH_SIZE 0x40000
#define DT_SRAM_SIZE 0x10000
#elif defined(CONFIG_SOC_STM32F334X8)
#define DT_FLASH_SIZE 0x10000
#define DT_SRAM_SIZE 0x3000
#elif defined(CONFIG_SOC_STM32F373XC)
#define DT_FLASH_SIZE 0x40000
#define DT_SRAM_SIZE 0x8000
#elif defined(CONFIG_SOC_STM32F401XE) || defined(CONFIG_SOC_STM32F411XE)
#define DT_FLASH_SIZE 0x80000
#define DT_SRAM_SIZE 0x18000
#elif defined(CONFIG_SOC_STM32L476XX)
#define DT_FLASH_SIZE 0x100000
#define DT_SRAM_SIZE 0x18000
#else
#error "Flash and RAM sizes not defined for this chip"
#endif
#endif /* __DT_BINDING_ST_MEM_H */

53
dts/arm/st/stm32f103xb.dtsi
View file

@ -16,20 +16,11 @@
reg = <0x20000000 DT_SRAM_SIZE>;
};
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
};
soc {
usart1: uart@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
interrupts = <37 0>;
baud-rate = <115200>;
status = "disabled";
};
@ -37,7 +28,6 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
interrupts = <38 0>;
baud-rate = <115200>;
status = "disabled";
};
@ -45,51 +35,8 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
interrupts = <39 0>;
baud-rate = <115200>;
status = "disabled";
};
pin-controller {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32f103xb-pinctrl";
ranges = <0 0x40010800 0x1400>;
gpioa: gpio@40010800 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x0 0x400>;
st,bank-name = "GPIOA";
};
gpiob: gpio@40010C00 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x400 0x400>;
st,bank-name = "GPIOB";
};
gpioc: gpio@40011000 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x800 0x400>;
st,bank-name = "GPIOC";
};
gpiod: gpio@40011400 {
gpio-controller;
#gpio-cells = <2>;
reg = <0xc00 0x400>;
st,bank-name = "GPIOD";
};
gpioe: gpio@40011800 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x1000 0x400>;
st,bank-name = "GPIOE";
};
};
};
};

45
dts/arm/st/stm32f103xe.dtsi Normal file
View file

@ -0,0 +1,45 @@
/*
* Copyright (c) 2017 I-SENSE group of ICCS
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <st/mem.h>
/ {
flash0: flash {
reg = <0x08000000 DT_FLASH_SIZE>;
};
sram0: memory {
reg = <0x20000000 DT_SRAM_SIZE>;
};
soc {
usart1: uart@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
interrupts = <37 0>;
status = "disabled";
};
usart2: uart@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
interrupts = <38 0>;
status = "disabled";
};
usart3: uart@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
interrupts = <39 0>;
status = "disabled";
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};

45
dts/arm/st/stm32f107.dtsi Normal file
View file

@ -0,0 +1,45 @@
/*
* Copyright (c) 2017 I-SENSE group of ICCS
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <st/mem.h>
/ {
flash0: flash {
reg = <0x08000000 DT_FLASH_SIZE>;
};
sram0: memory {
reg = <0x20000000 DT_SRAM_SIZE>;
};
soc {
usart1: uart@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
interrupts = <37 0>;
status = "disabled";
};
usart2: uart@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
interrupts = <38 0>;
status = "disabled";
};
usart3: uart@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
interrupts = <39 0>;
status = "disabled";
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};

45
dts/arm/st/stm32f334.dtsi Normal file
View file

@ -0,0 +1,45 @@
/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <st/mem.h>
/ {
flash0: flash {
reg = <0x08000000 DT_FLASH_SIZE>;
};
sram0: memory {
reg = <0x20000000 DT_SRAM_SIZE>;
};
soc {
usart1: uart@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
interrupts = <37 0>;
status = "disabled";
};
usart2: uart@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
interrupts = <38 0>;
status = "disabled";
};
usart3: uart@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
interrupts = <39 0>;
status = "disabled";
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};

45
dts/arm/st/stm32f373.dtsi Normal file
View file

@ -0,0 +1,45 @@
/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <st/mem.h>
/ {
flash0: flash {
reg = <0x08000000 DT_FLASH_SIZE>;
};
sram0: memory {
reg = <0x20000000 DT_SRAM_SIZE>;
};
soc {
usart1: uart@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
interrupts = <37 0>;
status = "disabled";
};
usart2: uart@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
interrupts = <38 0>;
status = "disabled";
};
usart3: uart@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
interrupts = <39 0>;
status = "disabled";
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};

45
dts/arm/st/stm32f4.dtsi Normal file
View file

@ -0,0 +1,45 @@
/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <st/mem.h>
/ {
flash0: flash {
reg = <0x08000000 DT_FLASH_SIZE>;
};
sram0: memory {
reg = <0x20000000 DT_SRAM_SIZE>;
};
soc {
usart1: uart@40011000 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011000 0x400>;
interrupts = <37 0>;
status = "disabled";
};
usart2: uart@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
interrupts = <38 0>;
status = "disabled";
};
usart6: uart@40011400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011400 0x400>;
interrupts = <71 0>;
status = "disabled";
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};

7
dts/arm/st/stm32f401.dtsi Normal file
View file

@ -0,0 +1,7 @@
/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/stm32f4.dtsi>

7
dts/arm/st/stm32f411.dtsi Normal file
View file

@ -0,0 +1,7 @@
/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/stm32f4.dtsi>

78
dts/arm/st/stm32l476.dtsi
View file

@ -16,20 +16,11 @@
reg = <0x20000000 DT_SRAM_SIZE>;
};
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
};
soc {
usart1: uart@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
interrupts = <37 0>;
baud-rate = <115200>;
status = "disabled";
};
@ -37,7 +28,6 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
interrupts = <38 0>;
baud-rate = <115200>;
status = "disabled";
};
@ -45,7 +35,6 @@
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
interrupts = <39 0>;
baud-rate = <115200>;
status = "disabled";
};
@ -53,7 +42,6 @@
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
interrupts = <52 0>;
baud-rate = <115200>;
status = "disabled";
};
@ -61,74 +49,8 @@
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
interrupts = <53 0>;
baud-rate = <115200>;
status = "disabled";
};
pin-controller {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32l4xx-pinctrl";
ranges = <0 0x48000000 0x2000>;
gpioa: gpio@48000000 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x0 0x400>;
st,bank-name = "GPIOA";
};
gpiob: gpio@48000400 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x400 0x400>;
st,bank-name = "GPIOB";
};
gpioc: gpio@48000800 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x800 0x400>;
st,bank-name = "GPIOC";
};
gpiod: gpio@48000c00 {
gpio-controller;
#gpio-cells = <2>;
reg = <0xc00 0x400>;
st,bank-name = "GPIOD";
};
gpioe: gpio@48001000 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x1000 0x400>;
st,bank-name = "GPIOE";
};
gpiof: gpio@48001400 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x1400 0x400>;
st,bank-name = "GPIOF";
};
gpiog: gpio@48001800 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x1800 0x400>;
st,bank-name = "GPIOG";
};
gpioh: gpio@48001c00 {
gpio-controller;
#gpio-cells = <2>;
reg = <0x1c00 0x400>;
st,bank-name = "GPIOH";
};
};
};
};