soc: st: add STM32L452XC
Adds STM32 L452 soc with L452xC variant. L452 has 160 KB SRAM; therefore, mpu mem config has been extended; IRQ number is based on 'stm32l452xx.h'. Signed-off-by: Georgij Cernysiov <g.cernysiov@elco-automation.de>
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5 changed files with 192 additions and 0 deletions
131
dts/arm/st/l4/stm32l452.dtsi
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131
dts/arm/st/l4/stm32l452.dtsi
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/*
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* Copyright (c) 2018 Georgij Cernysiov
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/l4/stm32l4.dtsi>
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/ {
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soc {
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pinctrl: pin-controller@48000000 {
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gpiod: gpio@48000c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
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label = "GPIOD";
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};
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gpioe: gpio@48001000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48001000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
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label = "GPIOE";
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};
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};
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usb: usb@40006800 {
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compatible = "st,stm32-usb";
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reg = <0x40006800 0x40000>;
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interrupts = <67 0>;
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interrupt-names = "usb";
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num-bidir-endpoints = <8>;
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ram-size = <1024>;
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phys = <&otgfs_phy>;
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status = "disabled";
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label = "USB";
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};
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i2c2: i2c@40005800 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
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interrupts = <33 0>, <34 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label= "I2C_2";
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};
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i2c4: i2c@40008400 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40008400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000002>;
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interrupts = <83 0>, <84 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label= "I2C_4";
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};
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spi2: spi@40003800 {
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compatible = "st,stm32-spi-fifo";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
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interrupts = <36 5>;
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status = "disabled";
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label = "SPI_2";
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};
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spi3: spi@40003C00 {
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compatible = "st,stm32-spi-fifo";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003C00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
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interrupts = <51 5>;
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status = "disabled";
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label = "SPI_3";
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};
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usart3: serial@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
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interrupts = <39 0>;
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status = "disabled";
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label = "UART_3";
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};
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uart4: serial@40004C00 {
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compatible = "st,stm32-uart";
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reg = <0x40004C00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
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interrupts = <52 0>;
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status = "disabled";
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label = "UART_4";
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};
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timers3: timers@40000400 {
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compatible = "st,stm32-timers";
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reg = <0x40000400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
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status = "disabled";
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label = "TIMERS_3";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <10000>;
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label = "PWM_3";
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#pwm-cells = <2>;
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};
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};
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};
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otgfs_phy: otgfs_phy {
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compatible = "usb-nop-xceiv";
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#phy-cells = <0>;
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label = "OTGFS_PHY";
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};
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};
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22
dts/arm/st/l4/stm32l452Xc.dtsi
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22
dts/arm/st/l4/stm32l452Xc.dtsi
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/*
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* Copyright (c) 2018 Georgij Cernysiov
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <st/l4/stm32l452.dtsi>
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/ {
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(160)>;
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};
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soc {
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flash-controller@40022000 {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_K(256)>;
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};
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};
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};
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};
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@ -57,6 +57,10 @@
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#define REGION_SRAM_0_SIZE REGION_64K
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#define REGION_SRAM_1_START 0x10000
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#define REGION_SRAM_1_SIZE REGION_64K
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#elif CONFIG_SRAM_SIZE == 160
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#define REGION_SRAM_0_SIZE REGION_128K
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#define REGION_SRAM_1_START 0x20000
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#define REGION_SRAM_1_SIZE REGION_32K
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#elif CONFIG_SRAM_SIZE == 192
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#define REGION_SRAM_0_SIZE REGION_128K
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#define REGION_SRAM_1_START 0x20000
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32
soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l452xx
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32
soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l452xx
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# Kconfig - ST Microelectronics STM32L452XX MCU
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#
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# Copyright (c) 2018 Georgij Cernysiov
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_STM32L452XC
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config SOC
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string
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default "stm32l452xx"
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config NUM_IRQS
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int
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default 85
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if GPIO_STM32
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config GPIO_STM32_PORTD
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default y
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config GPIO_STM32_PORTE
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default y
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config GPIO_STM32_PORTH
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default y
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endif # GPIO_STM32
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endif # SOC_STM32L452XC
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@ -22,6 +22,9 @@ config SOC_STM32L432XC
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config SOC_STM32L433XC
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bool "STM32L433XC"
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config SOC_STM32L452XC
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bool "STM32L452XC"
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config SOC_STM32L475XG
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bool "STM32L475XG"
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