arch: kinetis: Add support for k2x

This adds support for Kinestis K22

Co-authored-by: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
Co-authored-by: Oliver Stäbler <oliver.staebler@bytesatwork.ch>
Co-authored-by: Tom Burdick <thomas.burdick@gmail.com>
Signed-off-by: Tom Burdick <thomas.burdick@gmail.com>
This commit is contained in:
Tom Burdick 2019-09-12 08:41:26 -05:00 committed by Kumar Gala
commit 6a708e625d
14 changed files with 1010 additions and 1 deletions

361
dts/arm/nxp/nxp_k2x.dtsi Normal file
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@ -0,0 +1,361 @@
/*
* Copyright (c) 2018 Prevas A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/kinetis_sim.h>
#include <dt-bindings/clock/kinetis_mcg.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/i2c/i2c.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m4f";
reg = <0>;
};
};
/* The on-chip SRAM is split into SRAM_L and SRAM_U regions that form a
* contiguous block in the memory map, however misaligned accesses
* across the 0x2000_0000 boundary are not supported in the Arm
* Cortex-M4 architecture. For clarity and to avoid the temptation for
* someone to extend sram0 without solving this issue, we define two
* separate memory nodes here and only use the upper one for now. A
* potential solution has been proposed in binutils:
* https://sourceware.org/ml/binutils/2017-02/msg00250.html
*/
sram_l: memory@1fff0000 {
compatible = "mmio-sram";
reg = <0x1fff0000 0x10000>;
};
sram0: memory@20000000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x20000000 0x10000>;
};
soc {
mpu@4000d000 {
compatible = "nxp,k22f-mpu";
reg = <0x4000d000 0x824>;
status = "disabled";
};
mcg: clock-controller@40064000 {
compatible = "nxp,k22f-mcg";
reg = <0x40064000 0xd>;
system-clock-frequency = <120000000>;
clock-controller;
};
clock-controller@40065000 {
compatible = "nxp,k22f-osc";
reg = <0x40065000 0x4>;
enable-external-reference;
};
rtc@4003d000 {
compatible = "nxp,k22f-rtc";
reg = <0x4003d000 0x808>;
clock-frequency = <32768>;
};
sim: sim@40047000 {
compatible = "nxp,kinetis-sim";
reg = <0x40047000 0x1060>;
label = "SIM";
#clock-cells = <3>;
};
flash-controller@40020000 {
compatible = "nxp,kinetis-ftfe";
label = "FLASH_CTRL";
reg = <0x40020000 0x18>;
interrupts = <18 0>, <19 0>;
interrupt-names = "command-complete", "read-collision";
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@0 {
compatible = "soc-nv-flash";
label = "MCUX_FLASH";
reg = <0 0x100000>;
erase-block-size = <2048>;
write-block-size = <8>;
};
};
i2c0: i2c@40066000 {
compatible = "nxp,kinetis-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40066000 0x1000>;
interrupts = <24 0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>;
label = "I2C_0";
status = "disabled";
};
i2c1: i2c@40067000 {
compatible = "nxp,kinetis-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40067000 0x1000>;
interrupts = <25 0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 7>;
label = "I2C_1";
status = "disabled";
};
uart0: uart@4006a000 {
compatible = "nxp,kinetis-uart";
reg = <0x4006a000 0x1000>;
interrupts = <31 0>, <32 0>;
interrupt-names = "status", "error";
clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 10>;
label = "UART_0";
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
status = "disabled";
};
uart1: uart@4006b000 {
compatible = "nxp,kinetis-uart";
reg = <0x4006b000 0x1000>;
interrupts = <33 0>, <34 0>;
interrupt-names = "status", "error";
clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 11>;
label = "UART_1";
status = "disabled";
};
uart2: uart@4006c000 {
compatible = "nxp,kinetis-uart";
reg = <0x4006c000 0x1000>;
interrupts = <35 0>, <36 0>;
interrupt-names = "status", "error";
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 12>;
label = "UART_2";
status = "disabled";
};
uart3: uart@4006d000 {
compatible = "nxp,kinetis-uart";
reg = <0x4006d000 0x1000>;
interrupts = <37 0>, <38 0>;
interrupt-names = "status", "error";
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 13>;
label = "UART_3";
status = "disabled";
};
pinmux_a: pinmux@40049000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x40049000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
};
pinmux_b: pinmux@4004a000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004a000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
};
pinmux_c: pinmux@4004b000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004b000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
};
pinmux_d: pinmux@4004c000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004c000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
spi0_default: spi0_default {
miso-mosi-clk {
pins = <1>, <2>, <3>;
function = <2>;
};
};
};
pinmux_e: pinmux@4004d000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004d000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
uart0_default: uart0_default {
rx-tx {
pins = <0>, <1>;
function = <3>;
};
};
};
gpioa: gpio@400ff000 {
compatible = "nxp,kinetis-gpio";
reg = <0x400ff000 0x40>;
interrupts = <59 2>;
label = "GPIO_0";
gpio-controller;
#gpio-cells = <2>;
};
gpiob: gpio@400ff040 {
compatible = "nxp,kinetis-gpio";
reg = <0x400ff040 0x40>;
interrupts = <60 2>;
label = "GPIO_1";
gpio-controller;
#gpio-cells = <2>;
};
gpioc: gpio@400ff080 {
compatible = "nxp,kinetis-gpio";
reg = <0x400ff080 0x40>;
interrupts = <61 2>;
label = "GPIO_2";
gpio-controller;
#gpio-cells = <2>;
};
gpiod: gpio@400ff0c0 {
compatible = "nxp,kinetis-gpio";
reg = <0x400ff0c0 0x40>;
interrupts = <62 2>;
label = "GPIO_3";
gpio-controller;
#gpio-cells = <2>;
};
gpioe: gpio@400ff100 {
compatible = "nxp,kinetis-gpio";
reg = <0x400ff100 0x40>;
interrupts = <63 2>;
label = "GPIO_4";
gpio-controller;
#gpio-cells = <2>;
};
spi0: spi@4002c000 {
compatible = "nxp,kinetis-dspi";
reg = <0x4002c000 0x88>;
interrupts = <26 3>;
label = "SPI_0";
clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 12>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&spi0_default>;
pinctrl-names = "default";
};
spi1: spi@4002d000 {
compatible = "nxp,kinetis-dspi";
reg = <0x4002d000 0x88>;
interrupts = <27 3>;
label = "SPI_1";
clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 13>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
wdog: watchdog@40052000 {
compatible = "nxp,kinetis-wdog";
reg = <0x40052000 16>;
interrupts = <22 0>;
clocks = <&sim KINETIS_SIM_LPO_CLK 0 0>;
label = "WDT_0";
};
pwm0: pwm@40038000{
compatible = "nxp,kinetis-ftm";
reg = <0x40038000 0x98>;
interrupts = <42 0>;
label = "PWM_0";
status = "disabled";
#pwm-cells = <2>;
};
pwm1: pwm@40039000{
compatible = "nxp,kinetis-ftm";
reg = <0x40039000 0x98>;
interrupts = <43 0>;
label = "PWM_1";
status = "disabled";
#pwm-cells = <2>;
};
pwm2: pwm@4003a000{
compatible = "nxp,kinetis-ftm";
reg = <0x4003a000 0x98>;
interrupts = <44 0>;
label = "PWM_2";
status = "disabled";
#pwm-cells = <2>;
};
pwm3: pwm@400b9000{
compatible = "nxp,kinetis-ftm";
reg = <0x400b9000 0x98>;
interrupts = <71 0>;
label = "PWM_3";
status = "disabled";
#pwm-cells = <2>;
};
adc0: adc@4003b000{
compatible = "nxp,kinetis-adc16";
reg = <0x4003b000 0x70>;
interrupts = <39 0>;
label = "ADC_0";
status = "disabled";
#io-channel-cells = <1>;
};
usbd: usbd@40072000 {
compatible = "nxp,kinetis-usbd";
reg = <0x40072000 0x1000>;
interrupts = <53 1>;
interrupt-names = "usb_otg";
num-bidir-endpoints = <16>;
status = "disabled";
label = "USBD";
};
rnga: random@40029000 {
compatible = "nxp,kinetis-rnga";
reg = <0x40029000 0x1000>;
status = "okay";
interrupts = <23 0>;
label = "RNGA";
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};

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@ -147,4 +147,9 @@ config HAS_MCUX_PWM
help
Set if the PWM module is present in the SoC.
config HAS_MCUX_SMC
bool
help
Set if the SMC module is present in the SoC.
endif # HAS_MCUX

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@ -19,6 +19,7 @@ source "soc/arm/nxp_kinetis/*/Kconfig.soc"
config SOC_PART_NUMBER
string
default SOC_PART_NUMBER_KINETIS_K2X if SOC_SERIES_KINETIS_K2X
default SOC_PART_NUMBER_KINETIS_K6X if SOC_SERIES_KINETIS_K6X
default SOC_PART_NUMBER_KINETIS_K8X if SOC_SERIES_KINETIS_K8X
default SOC_PART_NUMBER_KINETIS_KWX if SOC_SERIES_KINETIS_KWX

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@ -0,0 +1,11 @@
#
# Copyright (c) 2018 Prevas A/S
#
# SPDX-License-Identifier: Apache-2.0
#
zephyr_sources(
soc.c
wdog.S
)

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@ -0,0 +1,101 @@
# Kconfig - FSL FRDM K22F platform configuration options
#
# Copyright (c) 2018 Prevas A/S
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_MK22F51212
config SOC
string
default "mk22f51212"
if ADC
config ADC_MCUX_ADC16
default y
endif # ADC
if CLOCK_CONTROL
config CLOCK_CONTROL_MCUX_SIM
default y
endif # CLOCK_CONTROL
if PINMUX
config PINMUX_MCUX
default y
endif # PINMUX
config GPIO
default y
if GPIO
config GPIO_MCUX
default y
endif # GPIO
if I2C
config I2C_MCUX
default y
endif # I2C
if PWM
config PWM_MCUX_FTM
default y
endif # PWM
if SPI
config SPI_MCUX_DSPI
default y
endif # SPI
if ENTROPY_GENERATOR
config ENTROPY_MCUX_RNGA
default y
endif # ENTROPY_GENERATOR
if FLASH
config SOC_FLASH_MCUX
default y
endif # FLASH
if SERIAL
config UART_MCUX
default y
endif # SERIAL
if USB
config USB_KINETIS
default y
endif # USB
if WATCHDOG
config WDT_MCUX_WDOG
default y
endif # WATCHDOG
endif # SOC_MK22F12

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@ -0,0 +1,21 @@
# Kconfig - Kinetis K2x series configuration options
#
# Copyright (c) 2018 Prevas A/S
# Copyright (c) 2019 Thomas Burdick <thomas.burdick@gmail.com>
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_SERIES_KINETIS_K2X
config SOC_SERIES
default "k2x"
config NUM_IRQS
int
default 74
source "soc/arm/nxp_kinetis/k2x/Kconfig.defconfig.mk*"
endif # SOC_SERIES_KINETIS_K2X

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@ -0,0 +1,17 @@
# Kconfig - Kinetis K2X MCU line
#
# Copyright (c) 2018 Prevas A/S
# Copyright (c) 2019 Thomas Burdick <thomas.burdick@gmail.com>
#
# SPDX-License-Identifier: Apache-2.0
#
config SOC_SERIES_KINETIS_K2X
bool "Kinetis K2x Series MCU"
select CPU_CORTEX_M4
select SOC_FAMILY_KINETIS
select CPU_HAS_NXP_MPU
select CLOCK_CONTROL
help
Enable support for Kinetis K2x MCU series

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@ -0,0 +1,82 @@
# Kconfig - Kinetis K2X MCU line
#
# Copyright (c) 2018 Prevas A/S
# Copyright (c) 2019 Thomas Burdick <thomas.burdick@gmail.com>
#
# SPDX-License-Identifier: Apache-2.0
#
choice
prompt "Kinetis K2x MCU Selection"
depends on SOC_SERIES_KINETIS_K2X
config SOC_MK22F51212
bool "SOC_MK22F51212"
select HAS_MCUX
select HAS_MCUX_SMC
select HAS_MCUX_ADC16
select HAS_MCUX_FTFX
select HAS_MCUX_FTM
select HAS_MCUX_RNGA
select HAS_MCUX_SIM
select HAS_OSC
select HAS_MCG
select HAS_CMSIS
select CPU_HAS_FPU
endchoice
if SOC_SERIES_KINETIS_K2X
config SOC_PART_NUMBER_MK22FN512VLH12
bool
config SOC_PART_NUMBER_MK22FX512AVLK12
bool
config SOC_PART_NUMBER_KINETIS_K2X
string
default "MK22FN512VLH12" if SOC_PART_NUMBER_MK22FN512VLH12
help
This string holds the full part number of the SoC. It is a hidden option
that you should not set directly. The part number selection choice defines
the default value for this string.
config K22_CORE_CLOCK_DIVIDER
int "Freescale K22 core clock divider"
default 1
help
This option specifies the divide value for the K22 processor core clock
from the system clock.
config K22_BUS_CLOCK_DIVIDER
int "Freescale K22 bus clock divider"
default 2
help
This option specifies the divide value for the K22 bus clock from the
system clock.
config K22_FLEXBUS_CLOCK_DIVIDER
int "Freescale K22 FlexBus clock divider"
default 3
help
This option specifies the divide value for the K22 FlexBus clock from the
system clock.
config K22_FLASH_CLOCK_DIVIDER
int "Freescale K22 flash clock divider"
default 3
help
This option specifies the divide value for the K64 flash clock from the
system clock.
config WDOG_INIT
def_bool y
# omit prompt to signify a "hidden" option
help
This processor enables the watchdog timer with a short timeout
upon reset. Therefore, this requires that the watchdog be configured
during reset handling.
endif # SOC_SERIES_KINETIS_K2X

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@ -0,0 +1,100 @@
/*
* Copyright (c) 2018 Prevas A/S
*
* SPDX-License-Identifier: Apache-2.0
*/
/* SoC level DTS fixup file */
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define DT_UART_MCUX_0_BAUD_RATE DT_NXP_KINETIS_UART_4006A000_CURRENT_SPEED
#define DT_UART_MCUX_0_NAME DT_NXP_KINETIS_UART_4006A000_LABEL
#define DT_UART_MCUX_0_IRQ_ERROR DT_NXP_KINETIS_UART_4006A000_IRQ_ERROR
#define DT_UART_MCUX_0_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_4006A000_IRQ_ERROR_PRIORITY
#define DT_UART_MCUX_0_IRQ_STATUS DT_NXP_KINETIS_UART_4006A000_IRQ_STATUS
#define DT_UART_MCUX_0_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_4006A000_IRQ_STATUS_PRIORITY
#define DT_UART_MCUX_0_CLOCK_NAME DT_NXP_KINETIS_UART_4006A000_CLOCK_CONTROLLER
#define DT_UART_MCUX_0_CLOCK_SUBSYS DT_NXP_KINETIS_UART_4006A000_CLOCK_NAME
#define DT_UART_MCUX_1_BAUD_RATE DT_NXP_KINETIS_UART_4006B000_CURRENT_SPEED
#define DT_UART_MCUX_1_NAME DT_NXP_KINETIS_UART_4006B000_LABEL
#define DT_UART_MCUX_1_IRQ_ERROR DT_NXP_KINETIS_UART_4006B000_IRQ_ERROR
#define DT_UART_MCUX_1_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_4006B000_IRQ_ERROR_PRIORITY
#define DT_UART_MCUX_1_IRQ_STATUS DT_NXP_KINETIS_UART_4006B000_IRQ_STATUS
#define DT_UART_MCUX_1_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_4006B000_IRQ_STATUS_PRIORITY
#define DT_UART_MCUX_1_HW_FLOW_CONTROL DT_NXP_KINETIS_UART_4006B000_HW_FLOW_CONTROL
#define DT_UART_MCUX_1_CLOCK_NAME DT_NXP_KINETIS_UART_4006B000_CLOCK_CONTROLLER
#define DT_UART_MCUX_1_CLOCK_SUBSYS DT_NXP_KINETIS_UART_4006B000_CLOCK_NAME
#define DT_UART_MCUX_2_BAUD_RATE DT_NXP_KINETIS_UART_4006C000_CURRENT_SPEED
#define DT_UART_MCUX_2_NAME DT_NXP_KINETIS_UART_4006C000_LABEL
#define DT_UART_MCUX_2_IRQ_ERROR DT_NXP_KINETIS_UART_4006C000_IRQ_ERROR
#define DT_UART_MCUX_2_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_4006C000_IRQ_ERROR_PRIORITY
#define DT_UART_MCUX_2_IRQ_STATUS DT_NXP_KINETIS_UART_4006C000_IRQ_STATUS
#define DT_UART_MCUX_2_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_4006C000_IRQ_STATUS_PRIORITY
#define DT_UART_MCUX_2_HW_FLOW_CONTROL DT_NXP_KINETIS_UART_4006C000_HW_FLOW_CONTROL
#define DT_UART_MCUX_2_CLOCK_NAME DT_NXP_KINETIS_UART_4006C000_CLOCK_CONTROLLER
#define DT_UART_MCUX_2_CLOCK_SUBSYS DT_NXP_KINETIS_UART_4006C000_CLOCK_NAME
#define DT_ADC_0_BASE_ADDRESS DT_NXP_KINETIS_ADC16_4003B000_BASE_ADDRESS
#define DT_ADC_0_IRQ DT_NXP_KINETIS_ADC16_4003B000_IRQ_0
#define DT_ADC_0_IRQ_PRI DT_NXP_KINETIS_ADC16_4003B000_IRQ_0_PRIORITY
#define DT_ADC_0_NAME DT_NXP_KINETIS_ADC16_4003B000_LABEL
#define DT_FTM_3_BASE_ADDRESS DT_NXP_KINETIS_FTM_400B9000_BASE_ADDRESS
#define DT_FTM_3_IRQ DT_NXP_KINETIS_FTM_400B9000_IRQ_0
#define DT_FTM_3_IRQ_PRI DT_NXP_KINETIS_FTM_400B9000_IRQ_0_PRIORITY
#define DT_FTM_3_NAME DT_NXP_KINETIS_FTM_400B9000_LABEL
#define DT_SIM_BASE_ADDRESS DT_NXP_KINETIS_SIM_40047000_BASE_ADDRESS
#define DT_SIM_NAME DT_NXP_KINETIS_SIM_40047000_LABEL
#define CONFIG_I2C_0_NAME DT_NXP_KINETIS_I2C_40066000_LABEL
#define DT_I2C_MCUX_0_BASE_ADDRESS DT_NXP_KINETIS_I2C_40066000_BASE_ADDRESS
#define DT_I2C_MCUX_0_IRQ DT_NXP_KINETIS_I2C_40066000_IRQ_0
#define DT_I2C_MCUX_0_IRQ_PRI DT_NXP_KINETIS_I2C_40066000_IRQ_0_PRIORITY
#define DT_I2C_MCUX_0_BITRATE DT_NXP_KINETIS_I2C_40066000_CLOCK_FREQUENCY
#define CONFIG_I2C_1_NAME DT_NXP_KINETIS_I2C_40067000_LABEL
#define DT_I2C_MCUX_1_BASE_ADDRESS DT_NXP_KINETIS_I2C_40067000_BASE_ADDRESS
#define DT_I2C_MCUX_1_IRQ DT_NXP_KINETIS_I2C_40067000_IRQ_0
#define DT_I2C_MCUX_1_IRQ_PRI DT_NXP_KINETIS_I2C_40067000_IRQ_0_PRIORITY
#define DT_I2C_MCUX_1_BITRATE DT_NXP_KINETIS_I2C_40067000_CLOCK_FREQUENCY
#define DT_FLASH_DEV_BASE_ADDRESS DT_NXP_KINETIS_FTFE_40020000_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_NXP_KINETIS_FTFE_40020000_LABEL
#define CONFIG_WDT_0_NAME DT_NXP_KINETIS_WDOG_40052000_LABEL
#define DT_WDT_0_BASE_ADDRESS DT_NXP_KINETIS_WDOG_40052000_BASE_ADDRESS
#define DT_WDT_0_IRQ DT_NXP_KINETIS_WDOG_40052000_IRQ_0
#define DT_WDT_0_IRQ_PRI DT_NXP_KINETIS_WDOG_40052000_IRQ_0_PRIORITY
#define DT_WDT_0_CLOCK_NAME DT_NXP_KINETIS_WDOG_40052000_CLOCK_CONTROLLER
#define DT_WDT_0_CLOCK_SUBSYS DT_NXP_KINETIS_WDOG_40052000_CLOCK_NAME
#define DT_SPI_0_NAME DT_NXP_KINETIS_DSPI_4002C000_LABEL
#define DT_SPI_0_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002C000_BASE_ADDRESS
#define DT_SPI_0_IRQ DT_NXP_KINETIS_DSPI_4002C000_IRQ_0
#define DT_SPI_0_IRQ_PRI DT_NXP_KINETIS_DSPI_4002C000_IRQ_0_PRIORITY
#define DT_SPI_0_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002C000_CLOCK_CONTROLLER
#define DT_SPI_0_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002C000_CLOCK_NAME
#define DT_SPI_1_NAME DT_NXP_KINETIS_DSPI_4002D000_LABEL
#define DT_SPI_1_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002D000_BASE_ADDRESS
#define DT_SPI_1_IRQ DT_NXP_KINETIS_DSPI_4002D000_IRQ_0
#define DT_SPI_1_IRQ_PRI DT_NXP_KINETIS_DSPI_4002D000_IRQ_0_PRIORITY
#define DT_SPI_1_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002D000_CLOCK_CONTROLLER
#define DT_SPI_1_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002D000_CLOCK_NAME
#define DT_USBD_KINETIS_NAME DT_NXP_KINETIS_USBD_40072000_LABEL
#define DT_USBD_KINETIS_IRQ DT_NXP_KINETIS_USBD_40072000_IRQ_USB_OTG
#define DT_USBD_KINETIS_IRQ_PRI DT_NXP_KINETIS_USBD_40072000_IRQ_USB_OTG_PRIORITY
#define DT_USBD_KINETIS_BASE_ADDRESS DT_NXP_KINETIS_USBD_40072000_BASE_ADDRESS
#define DT_USBD_KINETIS_NUM_BIDIR_EP DT_NXP_KINETIS_USBD_40072000_NUM_BIDIR_ENDPOINTS
#define DT_ENTROPY_MCUX_RNGA_BASE_ADDRESS DT_NXP_KINETIS_RNGA_40029000_BASE_ADDRESS
#define DT_ENTROPY_MCUX_RNGA_IRQ DT_NXP_KINETIS_RNGA_40029000_IRQ_0
#define DT_ENTROPY_MCUX_RNGA_IRQ_PRI DT_NXP_KINETIS_RNGA_40029000_IRQ_0_PRIORITY
#define DT_ENTROPY_MCUX_RNGA_NAME DT_NXP_KINETIS_RNGA_40029000_LABEL
#define CONFIG_ENTROPY_NAME DT_NXP_KINETIS_RNGA_40029000_LABEL
/* End of SoC Level DTS fixup file */

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@ -0,0 +1,14 @@
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Linker command/script file
*
* This is the linker script for both standard images and XIP images.
*/
#include <arch/arm/cortex_m/scripts/linker.ld>

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@ -0,0 +1,169 @@
/*
* Copyright (c) 2014-2015 Wind River Systems, Inc.
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright (c) 2018 Prevas A/S
* Copyright (c) 2019 Thomas Burdick <thomas.burdick@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief System/hardware module for fsl_frdm_k22f platform
*
* This module provides routines to initialize and support board-level
* hardware for the fsl_frdm_k22f platform.
*/
#include <kernel.h>
#include <device.h>
#include <init.h>
#include <soc.h>
#include <uart.h>
#include <fsl_common.h>
#include <fsl_clock.h>
#include <arch/cpu.h>
#include <cortex_m/exc.h>
#define PLLFLLSEL_MCGFLLCLK (0)
#define PLLFLLSEL_MCGPLLCLK (1)
#define PLLFLLSEL_IRC48MHZ (3)
#define ER32KSEL_OSC32KCLK (0)
#define ER32KSEL_RTC (2)
#define ER32KSEL_LPO1KHZ (3)
#define TIMESRC_OSCERCLK (2)
static const osc_config_t oscConfig = {
.freq = CONFIG_OSC_XTAL0_FREQ,
.capLoad = 0,
#if defined(CONFIG_OSC_EXTERNAL)
.workMode = kOSC_ModeExt,
#elif defined(CONFIG_OSC_LOW_POWER)
.workMode = kOSC_ModeOscLowPower,
#elif defined(CONFIG_OSC_HIGH_GAIN)
.workMode = kOSC_ModeOscHighGain,
#else
#error "An oscillator mode must be defined"
#endif
.oscerConfig = {
.enableMode = 0U, /* Disable external reference clock */
.erclkDiv = 0U,
},
};
static const mcg_pll_config_t pll0Config = {
.enableMode = 0U,
.prdiv = CONFIG_MCG_PRDIV0,
.vdiv = CONFIG_MCG_VDIV0,
};
static const sim_clock_config_t simConfig = {
.pllFllSel = PLLFLLSEL_MCGPLLCLK, /* PLLFLLSEL select PLL. */
.er32kSrc = ER32KSEL_RTC, /* ERCLK32K selection, use RTC. */
.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CONFIG_K22_CORE_CLOCK_DIVIDER - 1) |
SIM_CLKDIV1_OUTDIV2(CONFIG_K22_BUS_CLOCK_DIVIDER - 1) |
SIM_CLKDIV1_OUTDIV3(CONFIG_K22_FLEXBUS_CLOCK_DIVIDER - 1) |
SIM_CLKDIV1_OUTDIV4(CONFIG_K22_FLASH_CLOCK_DIVIDER - 1),
};
/**
*
* @brief Initialize the system clock
*
* This routine will configure the multipurpose clock generator (MCG) to
* set up the system clock.
* The MCG has nine possible modes, including Stop mode. This routine assumes
* that the current MCG mode is FLL Engaged Internal (FEI), as from reset.
* It transitions through the FLL Bypassed External (FBE) and
* PLL Bypassed External (PBE) modes to get to the desired
* PLL Engaged External (PEE) mode and generate the maximum 120 MHz system
* clock.
*
* @return N/A
*
*/
static ALWAYS_INLINE void clkInit(void)
{
CLOCK_SetSimSafeDivs();
CLOCK_InitOsc0(&oscConfig);
CLOCK_SetXtal0Freq(CONFIG_OSC_XTAL0_FREQ);
CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow,
CONFIG_MCG_FCRDIV);
/* Configure FLL external reference divider (FRDIV). */
CLOCK_SetFllExtRefDiv(0);
CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
CLOCK_SetSimConfig(&simConfig);
#if CONFIG_USB_KINETIS
CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0,
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
#endif
}
/**
*
* @brief Perform basic hardware initialization
*
* Initialize the interrupt controller device drivers.
* Also initialize the timer device driver, if required.
*
* @return 0
*/
static int fsl_frdm_k22f_init(struct device *arg)
{
ARG_UNUSED(arg);
unsigned int oldLevel; /* old interrupt lock level */
#if !defined(CONFIG_ARM_MPU)
#if defined(SYSMPU)
u32_t temp_reg;
#endif
#endif /* !CONFIG_ARM_MPU */
/* disable interrupts */
oldLevel = irq_lock();
/* release I/O power hold to allow normal run state */
PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
#if !defined(CONFIG_ARM_MPU)
/*
* Disable memory protection and clear slave port errors.
* Note that the K22F does not implement the optional ARMv7-M memory
* protection unit (MPU), specified by the architecture (PMSAv7), in the
* Cortex-M4 core. Instead, the processor includes its own MPU module.
*/
#if defined(SYSMPU)
temp_reg = SYSMPU->CESR;
temp_reg &= ~SYSMPU_CESR_VLD_MASK;
temp_reg |= SYSMPU_CESR_SPERR_MASK;
SYSMPU->CESR = temp_reg;
#endif
#endif /* !CONFIG_ARM_MPU */
/* Initialize PLL/system clock to 120 MHz */
clkInit();
/*
* install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();
/* restore interrupt state */
irq_unlock(oldLevel);
return 0;
}
SYS_INIT(fsl_frdm_k22f_init, PRE_KERNEL_1, 0);

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@ -0,0 +1,49 @@
/*
* Copyright (c) 2014-2015 Wind River Systems, Inc.
* Copyright (c) Thomas Burdick <thomas.burdick@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Board configuration macros for the fsl_frdm_k22f platform
*
* This header file is used to specify and describe board-level aspects for the
* 'fsl_frdm_k22f' platform.
*/
#ifndef _SOC__H_
#define _SOC__H_
#include <misc/util.h>
#ifdef __cplusplus
extern "C" {
#endif
/* default system clock */
#define SYSCLK_DEFAULT_IOSC_HZ MHZ(120)
#define BUSCLK_DEFAULT_IOSC_HZ (SYSCLK_DEFAULT_IOSC_HZ / \
CONFIG_K22_BUS_CLOCK_DIVIDER)
/* address bases */
#define PERIPH_ADDR_BASE_WDOG 0x40052000 /* Watchdog Timer module */
#ifndef _ASMLANGUAGE
#include <fsl_common.h>
#include <device.h>
#include <misc/util.h>
#include <random/rand32.h>
#endif /* !_ASMLANGUAGE */
#ifdef __cplusplus
}
#endif
#endif /* _SOC__H_ */

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@ -0,0 +1,78 @@
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief Watchdog initialization for fsl_frdm_k64f platform
*
* This module initializes the watchdog for the fsl_frdm_k64f platform.
*/
#include <soc.h>
#include <toolchain.h>
#include <linker/sections.h>
_ASM_FILE_PROLOGUE
GTEXT(_WdogInit)
/* watchdog register offsets */
#define WDOG_SCTRL_HI_OFFSET 0x0
#define WDOG_UNLOCK_OFFSET 0xE
/* watchdog command words */
#define WDOG_UNLOCK_1_CMD 0xC520
#define WDOG_UNLOCK_2_CMD 0xD928
/**
*
* @brief Watchdog timer disable routine
*
* This routine will disable the watchdog timer.
*
* @return N/A
*/
SECTION_FUNC(TEXT,_WdogInit)
/*
* NOTE: DO NOT SINGLE STEP THROUGH THIS FUNCTION!!!
* There are timing requirements for the execution of the unlock process.
* Single stepping through the code will cause the CPU to reset.
*/
/*
* First unlock the watchdog so that we can write to registers.
*
* This sequence must execute within 20 clock cycles, so disable
* interrupts to keep the code atomic and ensure the timing.
*/
cpsid i
ldr r0, =PERIPH_ADDR_BASE_WDOG
movw r1, #WDOG_UNLOCK_1_CMD
strh r1, [r0, #WDOG_UNLOCK_OFFSET]
movw r1, #WDOG_UNLOCK_2_CMD
strh r1, [r0, #WDOG_UNLOCK_OFFSET]
/*
* Disable the watchdog.
*
* Writes to control/configuration registers must execute within
* 256 clock cycles after unlocking.
*/
ldrh r1, [r0, #WDOG_SCTRL_HI_OFFSET]
mov r2, #1
bics r1, r2
strh r1, [r0, #WDOG_SCTRL_HI_OFFSET]
cpsie i
bx lr

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@ -83,7 +83,7 @@ manifest:
revision: bc62a2fa9d98ddb5d633c932ea199bc68e10f194
path: modules/fs/nffs
- name: hal_nxp
revision: 3eedd967c6ac4bce5f68309318ea8a78ae5751df
revision: 48a59fb436931d44d7595ec6deb42be41ff2f22b
path: modules/hal/nxp
- name: open-amp
revision: 9b591b289e1f37339bd038b5a1f0e6c8ad39c63a