soc: arm: nxp_imx: rt: add device support i.MX RT1010
- Add device support for i.MXRT1010 Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
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6 changed files with 171 additions and 1 deletions
85
dts/arm/nxp/nxp_rt1010.dtsi
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85
dts/arm/nxp/nxp_rt1010.dtsi
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/*
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* Copyright (c) 2019, Linaro
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <nxp/nxp_rt.dtsi>
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&sysclk {
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clock-frequency = <500000000>;
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};
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/* i.MX rt1010 default FlexRAM partition:
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* ITCM: 32KB
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* DTCM: 32KB
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* OCRAM: 64KB
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*/
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&itcm0 {
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reg = <0x00000000 0x8000>;
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};
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&dtcm0 {
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reg = <0x20000000 0x8000>;
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};
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&ocram0 {
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reg = <0x20200000 0x10000>;
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};
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&gpio1 {
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interrupts = <70 0>, <71 0>;
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};
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&gpio5 {
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interrupts = <73 0>;
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};
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&gpt1 {
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interrupts = <30 0>;
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};
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&gpt2 {
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interrupts = <31 0>;
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};
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&usbd1 {
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interrupts = <25 0>;
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};
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&flexspi0 {
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interrupts = <26 0>;
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};
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&flexpwm1_pwm0 {
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interrupts = <34 0>;
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};
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&flexpwm1_pwm1 {
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interrupts = <35 0>;
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};
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&flexpwm1_pwm2 {
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interrupts = <36 0>;
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};
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&flexpwm1_pwm3 {
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interrupts = <37 0>;
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};
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&flexpwm1 {
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interrupts = <38 0>;
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};
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/ {
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soc {
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gpio2_rt1010: gpio@42000000 {
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compatible = "nxp,imx-gpio";
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reg = <0x42000000 0x4000>;
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interrupts = <72 0>;
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label = "GPIO_2";
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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};
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35
soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1010
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35
soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1010
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# Kconfig - i.MX RT1010
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#
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# Copyright (c) 2019, NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_MIMXRT1011
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config SOC
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string
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default "mimxrt1011"
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config HAS_ARM_DIV
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default n
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config NUM_IRQS
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default 80
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config ARM_DIV
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default 0
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config AHB_DIV
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default 0
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config IPG_DIV
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default 3
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config GPIO
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default y
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config FLEXSPI_CONFIG_BLOCK_OFFSET
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default 0x400
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endif # SOC_MIMXRT1010
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@ -7,6 +7,25 @@ choice
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prompt "i.MX RT Selection"
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depends on SOC_SERIES_IMX_RT
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config SOC_MIMXRT1011
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bool "SOC_MIMXRT1011"
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select HAS_MCUX
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select HAS_MCUX_CACHE
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select HAS_MCUX_CCM
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select HAS_MCUX_IGPIO
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select HAS_MCUX_LPI2C
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select HAS_MCUX_LPSPI
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select HAS_MCUX_LPUART
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select HAS_MCUX_GPT
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select HAS_MCUX_TRNG
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select CPU_HAS_ARM_MPU
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select INIT_SYS_PLL
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select INIT_USB1_PLL
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select INIT_ENET_PLL
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select HAS_MCUX_USB_EHCI
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select HAS_MCUX_USDHC1
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select HAS_MCUX_USDHC2
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config SOC_MIMXRT1015
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bool "SOC_MIMXRT1015"
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select HAS_MCUX
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@ -170,6 +189,12 @@ endchoice
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if SOC_SERIES_IMX_RT
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config SOC_PART_NUMBER_MIMXRT1011CAE4A
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bool
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config SOC_PART_NUMBER_MIMXRT1011DAE5A
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bool
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config SOC_PART_NUMBER_MIMXRT1015CAF4A
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bool
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@ -232,6 +257,8 @@ config SOC_PART_NUMBER_MIMXRT1064DVL6A
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config SOC_PART_NUMBER_IMX_RT
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string
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default "MIMXRT1011CAE4A" if SOC_PART_NUMBER_MIMXRT1011CAE4A
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default "MIMXRT1011DAE5A" if SOC_PART_NUMBER_MIMXRT1011DAE5A
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default "MIMXRT1015CAF4A" if SOC_PART_NUMBER_MIMXRT1015CAF4A
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default "MIMXRT1015DAF5A" if SOC_PART_NUMBER_MIMXRT1015DAF5A
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default "MIMXRT1021CAF4A" if SOC_PART_NUMBER_MIMXRT1021CAF4A
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@ -276,6 +303,10 @@ config INIT_ENET_PLL
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MIMXRT1021 - see commit 17f4d6bec7 ("soc: nxp_imx: fix ENET_PLL selection
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for MIMXRT1021").
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config HAS_ARM_DIV
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bool "Has the divider for ARM"
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default y
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config ARM_DIV
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int "ARM clock divider"
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range 0 7
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@ -314,6 +345,15 @@ config BOOT_SEMC_NAND
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endchoice
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config FLEXSPI_CONFIG_BLOCK_OFFSET
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hex "FlexSPI config block offset"
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default 0x0 if BOOT_FLEXSPI_NOR
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help
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FlexSPI configuration block consists of parameters regarding specific
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flash devices including read command sequence, quad mode enablement
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sequence (optional), etc. The boot ROM expectes FlexSPI configuration
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parameter to be presented in serail nor flash.
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config IMAGE_VECTOR_TABLE_OFFSET
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hex "Image vector table offset"
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default 0x1000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR
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@ -5,6 +5,7 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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. = CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET;
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KEEP(*(.boot_hdr.conf))
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. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET;
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KEEP(*(.boot_hdr.ivt))
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@ -20,12 +20,19 @@
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#define DT_MCUX_IGPIO_1_IRQ_1 DT_NXP_IMX_GPIO_401B8000_IRQ_1
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#define DT_MCUX_IGPIO_1_IRQ_1_PRI DT_NXP_IMX_GPIO_401B8000_IRQ_1_PRIORITY
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#ifdef CONFIG_SOC_MIMXRT1011
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#define DT_MCUX_IGPIO_2_BASE_ADDRESS DT_NXP_IMX_GPIO_42000000_BASE_ADDRESS
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#define DT_MCUX_IGPIO_2_NAME DT_NXP_IMX_GPIO_42000000_LABEL
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#define DT_MCUX_IGPIO_2_IRQ_0 DT_NXP_IMX_GPIO_42000000_IRQ_0
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#define DT_MCUX_IGPIO_2_IRQ_0_PRI DT_NXP_IMX_GPIO_42000000_IRQ_0_PRIORITY
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#else
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#define DT_MCUX_IGPIO_2_BASE_ADDRESS DT_NXP_IMX_GPIO_401BC000_BASE_ADDRESS
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#define DT_MCUX_IGPIO_2_NAME DT_NXP_IMX_GPIO_401BC000_LABEL
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#define DT_MCUX_IGPIO_2_IRQ_0 DT_NXP_IMX_GPIO_401BC000_IRQ_0
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#define DT_MCUX_IGPIO_2_IRQ_0_PRI DT_NXP_IMX_GPIO_401BC000_IRQ_0_PRIORITY
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#define DT_MCUX_IGPIO_2_IRQ_1 DT_NXP_IMX_GPIO_401BC000_IRQ_1
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#define DT_MCUX_IGPIO_2_IRQ_1_PRI DT_NXP_IMX_GPIO_401BC000_IRQ_1_PRIORITY
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#endif
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#define DT_MCUX_IGPIO_3_BASE_ADDRESS DT_NXP_IMX_GPIO_401C0000_BASE_ADDRESS
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#define DT_MCUX_IGPIO_3_NAME DT_NXP_IMX_GPIO_401C0000_LABEL
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@ -49,7 +49,7 @@ const clock_usb_pll_config_t usb1PllConfig = {
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#ifdef CONFIG_INIT_ENET_PLL
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/* ENET PLL configuration for RUN mode */
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const clock_enet_pll_config_t ethPllConfig = {
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#if defined(CONFIG_SOC_MIMXRT1021) || defined(CONFIG_SOC_MIMXRT1015)
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#if defined(CONFIG_SOC_MIMXRT1021) || defined(CONFIG_SOC_MIMXRT1015) || defined(CONFIG_SOC_MIMXRT1011)
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.enableClkOutput500M = true,
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#endif
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#ifdef CONFIG_ETH_MCUX
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@ -145,7 +145,9 @@ static ALWAYS_INLINE void clock_init(void)
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CLOCK_InitVideoPll(&videoPllConfig);
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#endif
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#ifdef CONFIG_HAS_ARM_DIV
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CLOCK_SetDiv(kCLOCK_ArmDiv, CONFIG_ARM_DIV); /* Set ARM PODF */
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#endif
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CLOCK_SetDiv(kCLOCK_AhbDiv, CONFIG_AHB_DIV); /* Set AHB PODF */
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CLOCK_SetDiv(kCLOCK_IpgDiv, CONFIG_IPG_DIV); /* Set IPG PODF */
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