arch: arm: soc: stm32l0: add I2C support

Add SPI support for STM32L0 series.
L0 SPI peripheral requires SCK pin speed workaround
to function properly.

Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
This commit is contained in:
Ilya Tagunov 2018-03-15 15:23:10 +03:00 committed by Kumar Gala
commit 00c0520247
6 changed files with 89 additions and 0 deletions

View file

@ -32,4 +32,14 @@
#define CONFIG_I2C_3_COMBINED_IRQ ST_STM32_I2C_V2_40007800_IRQ_COMBINED
#define CONFIG_I2C_3_BITRATE ST_STM32_I2C_V2_40007800_CLOCK_FREQUENCY
#define CONFIG_SPI_1_BASE_ADDRESS ST_STM32_SPI_40013000_BASE_ADDRESS
#define CONFIG_SPI_1_IRQ_PRI ST_STM32_SPI_40013000_IRQ_0_PRIORITY
#define CONFIG_SPI_1_NAME ST_STM32_SPI_40013000_LABEL
#define CONFIG_SPI_1_IRQ ST_STM32_SPI_40013000_IRQ_0
#define CONFIG_SPI_2_BASE_ADDRESS ST_STM32_SPI_40003800_BASE_ADDRESS
#define CONFIG_SPI_2_IRQ_PRI ST_STM32_SPI_40003800_IRQ_0_PRIORITY
#define CONFIG_SPI_2_NAME ST_STM32_SPI_40003800_LABEL
#define CONFIG_SPI_2_IRQ ST_STM32_SPI_40003800_IRQ_0
/* End of SoC Level DTS fixup file */

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@ -46,6 +46,10 @@
#include <stm32l0xx_ll_i2c.h>
#endif
#ifdef CONFIG_SPI_STM32
#include <stm32l0xx_ll_spi.h>
#endif
#endif /* !_ASMLANGUAGE */
#endif /* _STM32L0_SOC_H_ */

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@ -51,4 +51,49 @@
#define STM32L0_PINMUX_FUNC_PC1_I2C3_SDA \
(STM32_PINMUX_ALT_FUNC_7 | STM32_OPENDRAIN_PULLUP)
/*
* Increase SCK pin speed to avoid last data bit corruption which is
* a known issue of STM32L0 SPI peripheral (see errata sheets).
*/
#define STM32L0_PINMUX_FUNC_PA4_SPI1_NSS \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)
#define STM32L0_PINMUX_FUNC_PA5_SPI1_SCK \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL | \
STM32_OSPEEDR_HIGH_SPEED)
#define STM32L0_PINMUX_FUNC_PA6_SPI1_MISO \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)
#define STM32L0_PINMUX_FUNC_PA7_SPI1_MOSI \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)
#define STM32L0_PINMUX_FUNC_PA15_SPI1_NSS \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)
#define STM32L0_PINMUX_FUNC_PB3_SPI1_SCK \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL | \
STM32_OSPEEDR_HIGH_SPEED)
#define STM32L0_PINMUX_FUNC_PB4_SPI1_MISO \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)
#define STM32L0_PINMUX_FUNC_PB5_SPI1_MOSI \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)
#define STM32L0_PINMUX_FUNC_PB12_SPI2_NSS \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)
#define STM32L0_PINMUX_FUNC_PB13_SPI2_SCK \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL | \
STM32_OSPEEDR_HIGH_SPEED)
#define STM32L0_PINMUX_FUNC_PB14_SPI2_MISO \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)
#define STM32L0_PINMUX_FUNC_PB15_SPI2_MOSI \
(STM32_PINMUX_ALT_FUNC_0 | STM32_PUSHPULL_NOPULL)
#define STM32L0_PINMUX_FUNC_PB9_SPI2_NSS \
(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL)
#define STM32L0_PINMUX_FUNC_PB10_SPI2_SCK \
(STM32_PINMUX_ALT_FUNC_5 | STM32_PUSHPULL_NOPULL | \
STM32_OSPEEDR_HIGH_SPEED)
#define STM32L0_PINMUX_FUNC_PC2_SPI2_MISO \
(STM32_PINMUX_ALT_FUNC_2 | STM32_PUSHPULL_NOPULL)
#define STM32L0_PINMUX_FUNC_PC3_SPI2_MOSI \
(STM32_PINMUX_ALT_FUNC_2 | STM32_PUSHPULL_NOPULL)
#endif /* _STM32L0_PINMUX_H_ */

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@ -91,6 +91,16 @@
status = "disabled";
label= "I2C_1";
};
spi1: spi@40013000 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013000 0x400>;
interrupts = <25 3>;
status = "disabled";
label = "SPI_1";
};
};
};

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@ -31,5 +31,15 @@
status = "disabled";
label= "I2C_3";
};
spi2: spi@40003800 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
interrupts = <26 3>;
status = "disabled";
label = "SPI_2";
};
};
};

View file

@ -31,5 +31,15 @@
status = "disabled";
label= "I2C_3";
};
spi2: spi@40003800 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
interrupts = <26 3>;
status = "disabled";
label = "SPI_2";
};
};
};