dts: nordic: nrf91: DTS include headers for nRF9160 SOC

This commit introduces the main device tree header files (.dtsi)
for Nordic nRF9160 SOC, for both Secure and Non-Secure domains.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit is contained in:
Ioannis Glaropoulos 2018-12-19 23:33:06 +01:00 committed by Carles Cufí
commit b3299891ed
5 changed files with 416 additions and 0 deletions

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/*
* Copyright (c) 2018 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv8-m.dtsi>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m33f";
reg = <0>;
};
};
sram0: memory@20000000 {
device_type = "memory";
compatible = "mmio-sram";
};
aliases {
flash-controller = &flash_controller;
ficr = &ficr;
rtc-1 = &rtc1;
clock = &clock;
power = &power;
nvmc = &nvmc;
spu = &spu;
uart-0 = &uart0;
uart-1 = &uart1;
uart-2 = &uart2;
uart-3 = &uart3;
adc-0 = &adc;
gpio-0 = &gpio0;
gpiote-0 = &gpiote;
i2c-0 = &i2c0;
i2c-1 = &i2c1;
i2c-2 = &i2c2;
i2c-3 = &i2c3;
spi-0 = &spi0;
spi-1 = &spi1;
spi-2 = &spi2;
spi-3 = &spi3;
wdt-0 = &wdt;
timer-0 = &timer0;
timer-1 = &timer1;
timer-2 = &timer2;
};
soc {
peripheral@50000000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x50000000 0x10000000>;
/* Common nRF9160 peripheral description */
#include "nrf9160_common.dtsi"
};
/* Addditional Secure peripherals */
gpiote: gpiote@5000d000 {
compatible = "nordic,nrf-gpiote";
reg = <0x5000d000 0x1000>;
interrupts = <13 5>;
status = "disabled";
label = "GPIOTE_0";
};
spu: spu@50003000 {
compatible = "nordic,nrf-spu";
reg = <0x50003000 0x1000>;
interrupts = <3 1>;
status = "ok";
};
ficr: ficr@ff0000 {
compatible = "nordic,nrf-ficr";
reg = <0xff0000 0x1000>;
status = "ok";
};
};
};
&nvic {
arm,num-irq-priority-bits = <3>;
};

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/*
* Copyright (c) 2018 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
flash_controller: flash-controller@39000 {
compatible = "nrf,nrf91-flash-controller";
reg = <0x39000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
label="NRF_FLASH_DRV_NAME";
flash0: flash@0 {
compatible = "soc-nv-flash";
label = "NRF_FLASH";
erase-block-size = <4096>;
write-block-size = <4>;
};
};
nvmc: nvmc@39000 {
compatible = "nordic,nrf-nvmc";
reg = <0x39000 0x1000>;
status = "ok";
label = "NVMC";
};
adc: adc@e000 {
compatible = "nordic,nrf-saadc";
reg = <0xe000 0x1000>;
interrupts = <14 1>;
status = "disabled";
label = "ADC_0";
};
uart0: uart@8000 {
compatible = "nordic,nrf-uarte";
reg = <0x8000 0x1000>;
interrupts = <8 1>;
status = "disabled";
label = "UART_0";
};
uart1: uart@9000 {
compatible = "nordic,nrf-uarte";
reg = <0x9000 0x1000>;
interrupts = <9 1>;
status = "disabled";
label = "UART_1";
};
uart2: uart@a000 {
compatible = "nordic,nrf-uarte";
reg = <0xa000 0x1000>;
interrupts = <10 1>;
status = "disabled";
label = "UART_2";
};
uart3: uart@b000 {
compatible = "nordic,nrf-uarte";
reg = <0xb000 0x1000>;
interrupts = <11 1>;
status = "disabled";
label = "UART_3";
};
i2c0: i2c@8000 {
compatible = "nordic,nrf-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x8000 0x1000>;
clock-frequency = <I2C_BITRATE_STANDARD>;
interrupts = <8 1>;
status = "disabled";
label = "I2C_0";
};
i2c1: i2c@9000 {
compatible = "nordic,nrf-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x9000 0x1000>;
clock-frequency = <I2C_BITRATE_STANDARD>;
interrupts = <9 1>;
status = "disabled";
label = "I2C_1";
};
i2c2: i2c@a000 {
compatible = "nordic,nrf-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xa000 0x1000>;
clock-frequency = <I2C_BITRATE_STANDARD>;
interrupts = <10 1>;
status = "disabled";
label = "I2C_2";
};
i2c3: i2c@b000 {
compatible = "nordic,nrf-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xb000 0x1000>;
clock-frequency = <I2C_BITRATE_STANDARD>;
interrupts = <11 1>;
status = "disabled";
label = "I2C_3";
};
spi0: spi@8000 {
compatible = "nordic,nrf-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x8000 0x1000>;
interrupts = <8 1>;
status = "disabled";
label = "SPI_0";
};
spi1: spi@9000 {
compatible = "nordic,nrf-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x9000 0x1000>;
interrupts = <9 1>;
status = "disabled";
label = "SPI_1";
};
spi2: spi@a000 {
compatible = "nordic,nrf-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xa000 0x1000>;
interrupts = <10 1>;
status = "disabled";
label = "SPI_2";
};
spi3: spi@b000 {
compatible = "nordic,nrf-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xb000 0x1000>;
interrupts = <11 1>;
status = "disabled";
label = "SPI_3";
};
gpio0: gpio@842500 {
compatible = "nordic,nrf-gpio";
gpio-controller;
reg = <0x842500 0x300>;
#gpio-cells = <2>;
label = "GPIO_0";
status = "disabled";
};
rtc1: rtc@15000 {
compatible = "nordic,nrf-rtc";
reg = <0x15000 0x1000>;
interrupts = <21 1>;
status = "ok";
};
clock: clock@5000 {
compatible = "nordic,nrf-clock";
reg = <0x5000 0x1000>;
interrupts = <5 1>;
status = "ok";
};
power: power@5000 {
compatible = "nordic,nrf-power";
reg = <0x5000 0x1000>;
interrupts = <5 1>;
status = "ok";
};
wdt: watchdog@18000 {
compatible = "nordic,nrf-watchdog";
reg = <0x18000 0x1000>;
interrupts = <24 1>;
label = "WDT";
};
timer0: timer@f000 {
compatible = "nordic,nrf-timer";
status = "disabled";
reg = <0xf000 0x1000>;
interrupts = <15 1>;
label = "TIMER0";
};
timer1: timer@10000 {
compatible = "nordic,nrf-timer";
status = "disabled";
reg = <0x10000 0x1000>;
interrupts = <16 1>;
label = "TIMER1";
};
timer2: timer@11000 {
compatible = "nordic,nrf-timer";
status = "disabled";
reg = <0x11000 0x1000>;
interrupts = <17 1>;
label = "TIMER2";
};

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/*
* Copyright (c) 2018 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <nordic/nrf9160.dtsi>
&flash0 {
reg = <0x00000000 DT_SIZE_K(1024)>;
};
&sram0 {
reg = <0x20000000 DT_SIZE_K(256)>;
};

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/*
* Copyright (c) 2018 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv8-m.dtsi>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m33f";
reg = <0>;
};
};
sram0: memory@20000000 {
device_type = "memory";
compatible = "mmio-sram";
};
aliases {
rtc-1 = &rtc1;
clock = &clock;
power = &power;
nvmc = &nvmc;
uart-0 = &uart0;
uart-1 = &uart1;
uart-2 = &uart2;
uart-3 = &uart3;
adc-0 = &adc;
gpio-0 = &gpio0;
gpiote-0 = &gpiote; /* FIXME alias should be gpiote-1 */
i2c-0 = &i2c0;
i2c-1 = &i2c1;
i2c-2 = &i2c2;
i2c-3 = &i2c3;
spi-0 = &spi0;
spi-1 = &spi1;
spi-2 = &spi2;
spi-3 = &spi3;
wdt-0 = &wdt;
timer-0 = &timer0;
timer-1 = &timer1;
timer-2 = &timer2;
};
soc {
peripheral@40000000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x40000000 0x10000000>;
/* Include common nRF9160 peripheral description */
#include "nrf9160_common.dtsi"
};
/* Addditional Non-Secure peripherals */
gpiote: gpiote@40031000 {
compatible = "nordic,nrf-gpiote";
reg = <0x40031000 0x1000>;
interrupts = <49 5>;
status = "disabled";
label = "GPIOTE_1";
};
};
};
&nvic {
arm,num-irq-priority-bits = <3>;
};

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/*
* Copyright (c) 2018 Nordic Semiconductor ASA
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <nordic/nrf9160ns.dtsi>
&flash0 {
reg = <0x00000000 DT_SIZE_K(1024)>;
};
&sram0 {
reg = <0x20000000 DT_SIZE_K(256)>;
};