soc: arm: st_stm32: Add STM32G4 SoC series
Add soc and dts files to support for most of the common peripherals in the STM32G4 series. Add specific support for the STM32G431RB. Signed-off-by: Richard Osterloh <richard.osterloh@gmail.com>
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34
dts/arm/st/g4/stm32g4.dtsi
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34
dts/arm/st/g4/stm32g4.dtsi
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/*
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* Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m4f";
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reg = <0>;
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};
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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soc {
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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7
dts/arm/st/g4/stm32g431.dtsi
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7
dts/arm/st/g4/stm32g431.dtsi
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/*
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* Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/g4/stm32g4.dtsi>
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22
dts/arm/st/g4/stm32g431Xb.dtsi
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22
dts/arm/st/g4/stm32g431Xb.dtsi
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/*
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* Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <st/g4/stm32g431.dtsi>
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/ {
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(32)>;
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};
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soc {
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flash-controller@40022000 {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_K(128)>;
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};
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};
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};
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};
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6
soc/arm/st_stm32/stm32g4/CMakeLists.txt
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6
soc/arm/st_stm32/stm32g4/CMakeLists.txt
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# SPDX-License-Identifier: Apache-2.0
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zephyr_include_directories(${ZEPHYR_BASE}/drivers)
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zephyr_sources(
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soc.c
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)
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15
soc/arm/st_stm32/stm32g4/Kconfig.defconfig.series
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15
soc/arm/st_stm32/stm32g4/Kconfig.defconfig.series
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# Kconfig - STMicroelectronics STM32G4 MCU line
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#
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# Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_SERIES_STM32G4X
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source "soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g4*"
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config SOC_SERIES
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default "stm32g4"
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endif # SOC_SERIES_STM32G4X
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21
soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g431rb
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21
soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g431rb
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# Kconfig - STMicroelectronics STM32G431RB MCU
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#
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# Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_STM32G431XX
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config SOC
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string
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default "stm32g431xx"
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config NUM_IRQS
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int
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default 102
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if GPIO_STM32
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endif # GPIO_STM32
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endif # SOC_STM32G431XX
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16
soc/arm/st_stm32/stm32g4/Kconfig.series
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soc/arm/st_stm32/stm32g4/Kconfig.series
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# Kconfig - STMicroelectronics STM32G4 MCU series
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#
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# Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config SOC_SERIES_STM32G4X
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bool "STM32G4x Series MCU"
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select CPU_CORTEX_M4
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select CPU_HAS_FPU
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select SOC_FAMILY_STM32
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select HAS_STM32CUBE
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select CPU_HAS_ARM_MPU
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help
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Enable support for STM32G4 MCU series
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15
soc/arm/st_stm32/stm32g4/Kconfig.soc
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15
soc/arm/st_stm32/stm32g4/Kconfig.soc
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# Kconfig - STMicroelectronics STM32G4 MCU line
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#
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# Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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choice
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prompt "STM32G4x MCU Selection"
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depends on SOC_SERIES_STM32G4X
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config SOC_STM32G431XX
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bool "STM32G431XX"
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endchoice
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11
soc/arm/st_stm32/stm32g4/dts_fixup.h
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11
soc/arm/st_stm32/stm32g4/dts_fixup.h
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/*
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* Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* SoC level DTS fixup file */
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#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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/* End of SoC Level DTS fixup file */
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9
soc/arm/st_stm32/stm32g4/linker.ld
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9
soc/arm/st_stm32/stm32g4/linker.ld
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/* linker.ld - Linker command/script file */
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/*
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* Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arch/arm/cortex_m/scripts/linker.ld>
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47
soc/arm/st_stm32/stm32g4/soc.c
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47
soc/arm/st_stm32/stm32g4/soc.c
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/*
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* Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for STM32G4 processor
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*/
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#include <device.h>
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#include <init.h>
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#include <arch/cpu.h>
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#include <cortex_m/exc.h>
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning.
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* So the init priority has to be 0 (zero).
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*
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* @return 0
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*/
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static int stm32g4_init(struct device *arg)
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{
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u32_t key;
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ARG_UNUSED(arg);
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key = irq_lock();
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/* Install default handler that simply resets the CPU
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* if configured in the kernel, NOP otherwise
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*/
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NMI_INIT();
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irq_unlock(key);
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/* Update CMSIS SystemCoreClock variable (HCLK) */
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/* At reset, system core clock is set to 16 MHz from HSI */
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SystemCoreClock = 16000000;
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return 0;
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}
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SYS_INIT(stm32g4_init, PRE_KERNEL_1, 0);
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32
soc/arm/st_stm32/stm32g4/soc.h
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32
soc/arm/st_stm32/stm32g4/soc.h
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/*
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* Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file SoC configuration macros for the STM32G4 family processors.
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*
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* Based on reference manual:
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* STM32G4xx advanced ARM ® -based 32-bit MCUs
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*
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* Chapter 2.2: Memory organization
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*/
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#ifndef _STM32G4_SOC_H_
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#define _STM32G4_SOC_H_
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#include <sys/util.h>
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#ifndef _ASMLANGUAGE
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#include <autoconf.h>
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#include <stm32g4xx.h>
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/* Add include for DTS generated information */
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#include <generated_dts_board.h>
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#endif /* !_ASMLANGUAGE */
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#endif /* _STM32G4_SOC_H_ */
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