boards: Add support for nulceo_wb55rg
Basic support for nucleo_wb55rg board. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
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3
boards/arm/nucleo_wb55rg/CMakeLists.txt
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3
boards/arm/nucleo_wb55rg/CMakeLists.txt
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zephyr_library()
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zephyr_library_sources(pinmux.c)
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zephyr_library_include_directories(${PROJECT_SOURCE_DIR}/drivers)
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10
boards/arm/nucleo_wb55rg/Kconfig.board
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boards/arm/nucleo_wb55rg/Kconfig.board
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# Kconfig - STM32WB55RG Nucleo board configuration
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#
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# Copyright (c) 2019 Linaro Limited
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config BOARD_NUCLEO_WB55RG
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bool "Nucleo WB55RG Development Board"
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depends on SOC_STM32WB55XG
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boards/arm/nucleo_wb55rg/Kconfig.defconfig
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boards/arm/nucleo_wb55rg/Kconfig.defconfig
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# Kconfig - STM32LWB55RG Nucleo board configuration
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#
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# Copyright (c) 2019 Linaro Limited
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if BOARD_NUCLEO_WB55RG
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config BOARD
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default "nucleo_wb55rg"
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if UART_CONSOLE
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config UART_1
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default y
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endif # UART_CONSOLE
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if BT_DEBUG_MONITOR
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config UART_1
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default y
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endif
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endif # BOARD_NUCLEO_WB55RG
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1
boards/arm/nucleo_wb55rg/board.cmake
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boards/arm/nucleo_wb55rg/board.cmake
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include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
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BIN
boards/arm/nucleo_wb55rg/doc/img/nucleowb55rg.jpg
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BIN
boards/arm/nucleo_wb55rg/doc/img/nucleowb55rg.jpg
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267
boards/arm/nucleo_wb55rg/doc/nucleowb55rg.rst
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boards/arm/nucleo_wb55rg/doc/nucleowb55rg.rst
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.. _nucleo_wb55rg_board:
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ST Nucleo WB55RG
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################
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Overview
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********
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The Nucleo WB55RG board is a multi-protocol wireless and ultra-low-power device
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embedding a powerful and ultra-low-power radio compliant with the Bluetooth®
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Low Energy (BLE) SIG specification v5.0 and with IEEE 802.15.4-2011.
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- STM32 microcontroller in VFQFPN68 package
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- 2.4 GHz RF transceiver supporting Bluetooth® specification v5.0 and
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IEEE 802.15.4-2011 PHY and MAC
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- Dedicated Arm® 32-bit Cortex® M0+ CPU for real-time Radio layer
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- Three user LEDs
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- Board connector: USB user with Micro-B
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- Two types of extension resources:
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- Arduino Uno V3 connectivity
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- ST morpho extension pin headers for full access to all STM32 I/Os
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- Integrated PCB antenna or footprint for SMA connector
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- On-board ST-LINK/V2-1 debugger/programmer with SWD connector
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- Flexible power-supply options: ST-LINK USB VBUS or external sources
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- On-board socket for CR2032 battery
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- On-board ST-LINK/V2-1 debugger/programmer with USB re- enumeration capability:
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mass storage, virtual COM port and debug port
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.. image:: img/nucleowb55rg.jpg
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:width: 670px
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:align: center
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:height: 339px
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:alt: Nucleo WB55RG
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More information about the board can be found at the `Nucleo WB55RG website`_.
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Hardware
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********
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STM32WB55RG is an ultra-low-power dual core Arm Cortex-M4 MCU 64 MHz,Cortex-M0 32MHz
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with 1 Mbyte of Flash memory, Bluetooth 5, 802.15.4, USB, LCD, AES-256 SoC and
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provides the following hardware capabilities:
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- Ultra-low-power with FlexPowerControl (down to 600 nA Standby mode with RTC and 32KB RAM)
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- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 64 MHz
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- Radio:
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- 2.4GHz
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- RF transceiver supporting Bluetooth® 5 specification, IEEE 802.15.4-2011 PHY and MAC,
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supporting Thread and ZigBee|reg| 3.0
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- RX Sensitivity: -96 dBm (Bluetooth|reg| Low Energy at 1 Mbps), -100 dBm (802.15.4)
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- Programmable output power up to +6 dBm with 1 dB steps
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- Integrated balun to reduce BOM
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- Support for 2 Mbps
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- Dedicated Arm|reg| 32-bit Cortex|reg| M0 + CPU for real-time Radio layer
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- Accurate RSSI to enable power control
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- Suitable for systems requiring compliance with radio frequency regulations
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ETSI EN 300 328, EN 300 440, FCC CFR47 Part 15 and ARIB STD-T66
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- Support for external PA
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- Clock Sources:
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- 32 MHz crystal oscillator with integrated trimming capacitors (Radio and CPU clock)
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- 32 kHz crystal oscillator for RTC (LSE)
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- 2x Internal low-power 32 kHz RC (|plusminus| 5% and |plusminus| 500ppm)
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- Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
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LSE (better than |plusminus| 0.25 % accuracy)
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- 2 PLLs for system clock, USB, SAI and ADC
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- RTC with HW calendar, alarms and calibration
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- LCD 8 x 40 or 4 x 44 with step-up converter
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- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors
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- 16x timers:
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- 2x 16-bit advanced motor-control
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- 2x 32-bit and 5x 16-bit general purpose
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- 2x 16-bit basic
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- 2x low-power 16-bit timers (available in Stop mode)
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- 2x watchdogs
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- SysTick timer
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- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V
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- Memories
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- Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection
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- Up to 320 KB of SRAM including 64 KB with hardware parity check
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- External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories
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- Quad SPI memory interface
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- 4x digital filters for sigma delta modulator
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- Rich analog peripherals (down to 1.62 V)
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- 12-bit ADC 4.26Msps, up to 16-bit with hardware oversampling, 200 uA/Msps
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- 2x ultra-low-power comparator
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- Accurate 2.5 V or 2.048 V reference voltage buffered output
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- System peripherals
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- Inter processor communication controller (IPCC) for communication with
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Bluetooth|reg| Low Energy and 802.15.4
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- HW semaphores for resources sharing between CPUs
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- 2x DMA controllers (7x channels each) supporting ADC, SPI, I2C, USART,
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QSPI, SAI, AES, Timers
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- 1x USART (ISO 7816, IrDA, SPI Master, Modbus and Smartcard mode)
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- 1x LPUART (low power)
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- 2x SPI 32 Mbit/s
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- 2x I2C (SMBus/PMBus)
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- 1x SAI (dual channel high quality audio)
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- 1x USB 2.0 FS device, crystal-less, BCD and LPM
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- Touch sensing controller, up to 18 sensors
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- LCD 8x40 with step-up converter
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- 1x 16-bit, four channels advanced timer
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- 2x 16-bits, two channels timer
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- 1x 32-bits, four channels timer
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- 2x 16-bits ultra-low-power timer
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- 1x independent Systick
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- 1x independent watchdog
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- 1x window watchdog
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- Security and ID
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- 3x hardware encryption AES maximum 256-bit for the application,
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the Bluetooth|reg| Low Energy and IEEE802.15.4
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- Customer key storage / key manager services
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- HW public key authority (PKA)
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- Cryptographic algorithms: RSA, Diffie-Helman, ECC over GF(p)
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- True random number generator (RNG)
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- Sector protection against R/W operation (PCROP)
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- CRC calculation unit
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- 96-bit unique ID
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- 64-bit unique ID. Possibility to derive 802.15.5 64-bit and
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Bluetooth|reg| Low Energy 48-bit EUI
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- Up to 72 fast I/Os, 70 of them 5 V-tolerant
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- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade|
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More information about STM32WB55RG can be found here:
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- `STM32WB55RG on www.st.com`_
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- `STM32WB5RG datasheet`_
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Supported Features
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==================
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The Zephyr nucleo_wb55rg board configuration supports the following hardware features:
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+-----------+------------+-------------------------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+=====================================+
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| NVIC | on-chip | nested vector interrupt controller |
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+-----------+------------+-------------------------------------+
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| UART | on-chip | serial port-polling; |
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| | | serial port-interrupt |
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+-----------+------------+-------------------------------------+
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| PINMUX | on-chip | pinmux |
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+-----------+------------+-------------------------------------+
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| GPIO | on-chip | gpio |
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+-----------+------------+-------------------------------------+
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Other hardware features are not yet supported on this Zephyr port.
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The default configuration can be found in the defconfig file:
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``boards/arm/nucleo_wb55rg/nucleo_wb55rg_defconfig``
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Connections and IOs
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===================
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Nucleo WB55RG Board has 6 GPIO controllers. These controllers are responsible for pin muxing,
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input/output, pull-up, etc.
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Default Zephyr Peripheral Mapping:
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----------------------------------
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- UART_1 TX/RX : PB7/PB6
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- USER_PB : PC4
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- USER_PB1 : PD0
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- USER_PB2 : PD1
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- LD1 : PB5
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- LD2 : PB0
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- LD3 : PB1
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System Clock
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------------
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Nucleo WB55RG System Clock could be driven by internal or external oscillator,
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as well as main PLL clock. By default System clock is driven by HSE clock at 32MHz.
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Serial Port
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-----------
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Nucleo WB55RG board has 2 (LP)U(S)ARTs. The Zephyr console output is assigned to USART1.
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Default settings are 115200 8N1.
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Programming and Debugging
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*************************
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Applications for the ``nucleo_wb55rg`` board configuration can be built the
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usual way (see :ref:`build_an_application`).
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Flashing
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========
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Nucleo WB55RG board includes an ST-LINK/V2-1 embedded debug tool
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interface. This interface is not yet supported by the openocd version
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included in the Zephyr SDK. You can flash your application with drag and drop
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in the drive mounted when plugging your nucleo board to your PC.
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Flashing an application to Nucleo WB55RG
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----------------------------------------
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Connect the Nucleo WB55RG to your host computer using the USB port.
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Then build and flash an application. Here is an example for the
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:ref:`hello_world` application.
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Run a serial host program to connect with your Nucleo board:
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.. code-block:: console
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$ minicom -D /dev/ttyUSB0
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Then build and flash the application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: nucleo_wb55rg
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:goals: build
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You should see the following message on the console:
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.. code-block:: console
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Hello World! arm
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Debugging
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=========
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While STM32WB55RG is not yet supported you can debug an application using pyocd.
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Here is an example for the :ref:`hello_world` application.
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Start pyocd gdbserver on your machine:
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.. code-block:: console
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$ pyocd gdbserver
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Then launch debug on your board:
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: nucleo_wb55rg
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:maybe-skip-config:
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:goals: debug
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.. _Nucleo WB55RG website:
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https://www.st.com/en/evaluation-tools/p-nucleo-wb55.html
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.. _STM32WB55RG on www.st.com:
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https://www.st.com/en/microcontrollers-microprocessors/stm32wb55rg.html
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.. _STM32WB5RG datasheet:
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https://www.st.com/resource/en/datasheet/stm32wb55rg.pdf
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63
boards/arm/nucleo_wb55rg/nucleo_wb55rg.dts
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boards/arm/nucleo_wb55rg/nucleo_wb55rg.dts
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/*
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* Copyright (c) 2019 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <st/wb/stm32wb55Xg.dtsi>
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/ {
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model = "STMicroelectronics STM32WB55RG-NUCLEO board";
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compatible = "st,stm32wb55rg-nucleo", "st,stm32wb55rg";
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chosen {
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zephyr,console = &usart1;
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zephyr,shell-uart = &usart1;
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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};
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leds {
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compatible = "gpio-leds";
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blue_led_1: led_0 {
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gpios = <&gpiob 5 GPIO_INT_ACTIVE_HIGH>;
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label = "User LED1";
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};
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green_led_2: led_1 {
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gpios = <&gpiob 0 GPIO_INT_ACTIVE_HIGH>;
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label = "User LED2";
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};
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green_led_3: led_2 {
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gpios = <&gpiob 1 GPIO_INT_ACTIVE_HIGH>;
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label = "User LED3";
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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user_button_1: button_0 {
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label = "SW1";
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gpios = <&gpioc 4 GPIO_INT_ACTIVE_LOW>;
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};
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user_button_2: button_1 {
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label = "SW2";
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gpios = <&gpiod 0 GPIO_INT_ACTIVE_LOW>;
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};
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user_button_3: button_2 {
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label = "SW3";
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gpios = <&gpiod 1 GPIO_INT_ACTIVE_LOW>;
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};
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};
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aliases {
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led0 = &green_led_2;
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sw0 = &user_button_1;
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sw1 = &user_button_2;
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};
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};
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&usart1 {
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current-speed = <115200>;
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status = "ok";
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};
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12
boards/arm/nucleo_wb55rg/nucleo_wb55rg.yaml
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12
boards/arm/nucleo_wb55rg/nucleo_wb55rg.yaml
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identifier: nucleo_wb55rg
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name: NUCLEO-WB55RG
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type: mcu
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arch: arm
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toolchain:
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- zephyr
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- gccarmemb
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- xtools
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ram: 96
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flash: 1024
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supported:
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- gpio
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36
boards/arm/nucleo_wb55rg/nucleo_wb55rg_defconfig
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36
boards/arm/nucleo_wb55rg/nucleo_wb55rg_defconfig
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CONFIG_ARM=y
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CONFIG_SOC_SERIES_STM32WBX=y
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CONFIG_SOC_STM32WB55XG=y
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CONFIG_CORTEX_M_SYSTICK=y
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# 32MHz system clock
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000000
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CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
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# enable uart driver
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CONFIG_SERIAL=y
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# enable pinmux
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CONFIG_PINMUX=y
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# enable GPIO
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CONFIG_GPIO=y
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# clock configuration
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CONFIG_CLOCK_CONTROL=y
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# SYSCLK selection
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#CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
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CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y
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CONFIG_CLOCK_STM32_HSE_CLOCK=32000000
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CONFIG_CLOCK_STM32_CPU1_PRESCALER=1
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CONFIG_CLOCK_STM32_CPU2_PRESCALER=1
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CONFIG_CLOCK_STM32_APB1_PRESCALER=1
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CONFIG_CLOCK_STM32_APB2_PRESCALER=1
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CONFIG_CLOCK_STM32_AHB4_PRESCALER=1
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# console
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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# Enable MPU
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CONFIG_ARM_MPU=y
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33
boards/arm/nucleo_wb55rg/pinmux.c
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33
boards/arm/nucleo_wb55rg/pinmux.c
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/*
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* Copyright (c) 2018 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <pinmux.h>
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#include <sys_io.h>
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#include <pinmux/stm32/pinmux_stm32.h>
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/* pin assignments for NUCLEO-WB55RG board */
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static const struct pin_config pinconf[] = {
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#ifdef CONFIG_UART_1
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{STM32_PIN_PB7, STM32WBX_PINMUX_FUNC_PB7_USART1_RX},
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{STM32_PIN_PB6, STM32WBX_PINMUX_FUNC_PB6_USART1_TX},
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#endif /* CONFIG_UART_1 */
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};
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static int pinmux_stm32_init(struct device *port)
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{
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ARG_UNUSED(port);
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stm32_setup_pins(pinconf, ARRAY_SIZE(pinconf));
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|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(pinmux_stm32_init, PRE_KERNEL_1,
|
||||
CONFIG_PINMUX_STM32_DEVICE_INITIALIZATION_PRIORITY);
|
30
dts/arm/st/wb/stm32wb55Xg.dtsi
Normal file
30
dts/arm/st/wb/stm32wb55Xg.dtsi
Normal file
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <mem.h>
|
||||
#include <st/wb/stm32wb55.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(96)>;
|
||||
};
|
||||
|
||||
sram2a:memory@20030000 {
|
||||
reg = <0x20030000 0x2800>;
|
||||
};
|
||||
|
||||
sram2b:memory@20038000 {
|
||||
reg = <0x20038000 0x5000>;
|
||||
};
|
||||
|
||||
|
||||
soc {
|
||||
flash-controller@58004000 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(1024)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
Loading…
Add table
Add a link
Reference in a new issue