dts: xilinx_zynqmp: Refactor dts to specify RPU and APU separately.
ZynqMP SoC embeds two separate processor types: Cortex-R for RPU and Cortex-A for APU. Since the current Zephyr architecture cannot support AMP of Cortex-R and Cortex-A within one project, the RPU and APU should be considered separate platforms. This commit relocates the device tree nodes that are not common between RPU and APU to a separate dtsi file (zynqmp_rpu.dtsi). When Cortex-A53 APU support is added in the future, an additional dtsi file (zynqmp_apu.dtsi) for specifying the APU device tree should be added. For more details, refer to the issue #20217. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
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3 changed files with 35 additions and 24 deletions
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@ -6,7 +6,7 @@
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*/
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/dts-v1/;
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#include <arm/xilinx/zynqmp.dtsi>
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#include <arm/xilinx/zynqmp_rpu.dtsi>
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/ {
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model = "QEMU Cortex-R5";
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@ -9,30 +9,7 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-r4";
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reg = <0>;
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};
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};
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soc {
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interrupt-parent = <&gic>;
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gic: interrupt-controller@f9010000 {
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compatible = "arm,gic";
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reg = <0xf9010000 0x1000>,
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<0xf9020000 0x100>;
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interrupt-controller;
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#interrupt-cells = <4>;
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label = "GIC";
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status = "okay";
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};
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flash0: flash@c0000000 {
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compatible = "soc-nv-flash";
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reg = <0xc0000000 DT_SIZE_K(64)>;
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34
dts/arm/xilinx/zynqmp_rpu.dtsi
Normal file
34
dts/arm/xilinx/zynqmp_rpu.dtsi
Normal file
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@ -0,0 +1,34 @@
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/*
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* Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/xilinx/zynqmp.dtsi>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-r4";
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reg = <0>;
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};
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};
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soc {
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interrupt-parent = <&gic>;
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gic: interrupt-controller@f9010000 {
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compatible = "arm,gic";
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reg = <0xf9010000 0x1000>,
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<0xf9020000 0x100>;
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interrupt-controller;
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#interrupt-cells = <4>;
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label = "GIC";
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status = "okay";
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};
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};
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};
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