dts: arm: st: Factorize STM32F3 series soc dtsi files
In order to simplify maintenance of dts files for stm32f1 series, introduce a stm32f3.dtsi file which represent the smallest common denominator of IPs in the family. Besides, stm32f334 includes stm32f303, as it is a extension of this SoC. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou
Kumar Gala
parent
851efe0cc6
commit
9f88663079
4 changed files with 76 additions and 201 deletions
73
dts/arm/st/stm32f3.dtsi
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73
dts/arm/st/stm32f3.dtsi
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/*
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* Copyright (c) 2017 I-SENSE group of ICCS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <st/mem.h>
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#include <dt-bindings/clock/stm32_clock.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m4f";
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reg = <0>;
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};
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};
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flash0: flash@8000000 {
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reg = <0x08000000 DT_FLASH_SIZE>;
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};
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sram0: memory@20000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SRAM_SIZE>;
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};
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soc {
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rcc: rcc@40021000 {
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compatible = "st,stm32-rcc";
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clocks-controller;
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#clocks-cells = <2>;
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reg = <0x40021000 0x400>;
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label = "STM32_CLK_RCC";
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};
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usart1: serial@40013800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40013800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
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interrupts = <37 0>;
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status = "disabled";
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label = "UART_1";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
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interrupts = <38 0>;
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status = "disabled";
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label = "UART_2";
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};
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usart3: serial@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
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interrupts = <39 0>;
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status = "disabled";
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label = "UART_3";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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@ -4,70 +4,4 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <st/mem.h>
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#include <dt-bindings/clock/stm32_clock.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m4f";
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reg = <0>;
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};
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};
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flash0: flash@8000000 {
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reg = <0x08000000 DT_FLASH_SIZE>;
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};
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sram0: memory@20000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SRAM_SIZE>;
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};
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soc {
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rcc: rcc@40021000 {
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compatible = "st,stm32-rcc";
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clocks-controller;
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#clocks-cells = <2>;
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reg = <0x40021000 0x400>;
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label = "STM32_CLK_RCC";
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};
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usart1: serial@40013800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40013800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
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interrupts = <37 0>;
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status = "disabled";
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label = "UART_1";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
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interrupts = <38 0>;
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status = "disabled";
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label = "UART_2";
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};
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usart3: serial@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
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interrupts = <39 0>;
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status = "disabled";
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label = "UART_3";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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#include <st/stm32f3.dtsi>
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@ -4,70 +4,4 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <st/mem.h>
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#include <dt-bindings/clock/stm32_clock.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m4f";
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reg = <0>;
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};
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};
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flash0: flash@8000000 {
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reg = <0x08000000 DT_FLASH_SIZE>;
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};
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sram0: memory@20000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SRAM_SIZE>;
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};
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soc {
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rcc: rcc@40021000 {
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compatible = "st,stm32-rcc";
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clocks-controller;
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#clocks-cells = <2>;
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reg = <0x40021000 0x400>;
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label = "STM32_CLK_RCC";
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};
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usart1: serial@40013800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40013800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
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interrupts = <37 0>;
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status = "disabled";
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label = "UART_1";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
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interrupts = <38 0>;
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status = "disabled";
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label = "UART_2";
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};
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usart3: serial@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
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interrupts = <39 0>;
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status = "disabled";
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label = "UART_3";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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#include <st/stm32f303.dtsi>
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@ -4,70 +4,4 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <st/mem.h>
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#include <dt-bindings/clock/stm32_clock.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m4f";
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reg = <0>;
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};
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};
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flash0: flash@8000000 {
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reg = <0x08000000 DT_FLASH_SIZE>;
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};
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sram0: memory@20000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SRAM_SIZE>;
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};
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soc {
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rcc: rcc@40021000 {
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compatible = "st,stm32-rcc";
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clocks-controller;
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#clocks-cells = <2>;
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reg = <0x40021000 0x400>;
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label = "STM32_CLK_RCC";
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};
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usart1: serial@40013800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40013800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
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interrupts = <37 0>;
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status = "disabled";
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label = "UART_1";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
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interrupts = <38 0>;
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status = "disabled";
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label = "UART_2";
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};
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usart3: serial@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
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interrupts = <39 0>;
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status = "disabled";
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label = "UART_3";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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#include <st/stm32f3.dtsi>
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