lpc: Add nxp_lpc soc family to soc directory

Add soc configuration support for lpc soc family, Kconfigs and soc files
for lpcxxx soc.

Add dtsi file for lpc54xxx.

Signed-off-by: Shiksha Patel <shiksha.patel@nxp.com>
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>

arch/arm/soc/nxp_lpc/CMakeLists.txt

@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+add_subdirectory(${SOC_SERIES})

arch/arm/soc/nxp_lpc/Kconfig

@@ -0,0 +1,27 @@
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_FAMILY_LPC
+	bool
+	# omit prompt to signify a "hidden" option
+	default n
+
+if SOC_FAMILY_LPC
+config SOC_FAMILY
+	string
+	default "nxp_lpc"
+endif
+
+source "arch/arm/soc/nxp_lpc/*/Kconfig.soc"
+
+config SOC_PART_NUMBER
+	string
+	default SOC_PART_NUMBER_LPC54XXX if SOC_SERIES_LPC54XXX
+
+	help
+	  This string holds the full part number of the SoC. It is a hidden option
+	  that you should not set directly. The part number selection choice defines
+	  the default value for this string.

arch/arm/soc/nxp_lpc/Kconfig.defconfig

@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+source "arch/arm/soc/nxp_lpc/*/Kconfig.defconfig.series"

arch/arm/soc/nxp_lpc/Kconfig.soc

@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+source "arch/arm/soc/nxp_lpc/*/Kconfig.series"

arch/arm/soc/nxp_lpc/lpc54xxx/CMakeLists.txt

@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_sources(
+  soc.c
+  )

arch/arm/soc/nxp_lpc/lpc54xxx/Kconfig.defconfig.lpc54114

@@ -0,0 +1,35 @@
+# Kconfig - NXP LPC54114 platform configuration options
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_LPC54114
+
+config SOC
+	string
+	default lpc54114
+
+if PINMUX
+
+config PINMUX_MCUX_LPC
+	def_bool y
+
+endif # PINMUX
+
+if GPIO
+
+config GPIO_MCUX_LPC
+	def_bool y
+
+endif # GPIO
+
+if SERIAL
+
+config USART_MCUX_LPC
+	def_bool y
+
+endif # SERIAL
+
+endif # SOC_LPC54114

arch/arm/soc/nxp_lpc/lpc54xxx/Kconfig.defconfig.series

@@ -0,0 +1,20 @@
+# Kconfig -  LPC54XXX series configuration options
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_SERIES_LPC54XXX
+
+config SOC_SERIES
+	default lpc54xxx
+
+config NUM_IRQS
+	int
+	# must be >= the highest interrupt number used
+	default 40
+
+source "arch/arm/soc/nxp_lpc/lpc54xxx/Kconfig.defconfig.lp*"
+
+endif # SOC_SERIES_LPC54XXX

arch/arm/soc/nxp_lpc/lpc54xxx/Kconfig.series

@@ -0,0 +1,16 @@
+# Kconfig - LPC LPC54XXX MCU line
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_SERIES_LPC54XXX
+	bool "LPC LPC54xxx Series MCU"
+	select CPU_CORTEX_M
+	select CPU_CORTEX_M4
+	select SOC_FAMILY_LPC
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	select CPU_HAS_SYSTICK
+	help
+	  Enable support for LPC LPC54XXX MCU series

arch/arm/soc/nxp_lpc/lpc54xxx/Kconfig.soc

@@ -0,0 +1,32 @@
+# Kconfig - LPC LPC54XXX MCU line
+#
+# Copyright (c) 2017, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+choice
+prompt "LPC LPC54XXX MCU Selection"
+depends on SOC_SERIES_LPC54XXX
+
+config SOC_LPC54114
+	bool "SOC_LPC54114"
+	select HAS_MCUX
+
+endchoice
+
+if SOC_SERIES_LPC54XXX
+
+config SOC_PART_NUMBER_LPC54114J256BD64
+	bool
+
+config SOC_PART_NUMBER_LPC54XXX
+	string
+	default "LPC54114J256BD64" if SOC_PART_NUMBER_LPC54114J256BD64
+
+	help
+	  This string holds the full part number of the SoC. It is a hidden
+	  option that you should not set directly. The part number selection
+	  choice defines the default value for this string.
+
+endif # SOC_SERIES_LPC54XXX

arch/arm/soc/nxp_lpc/lpc54xxx/linker.ld

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2014 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Linker command/script file
+ *
+ * This is the linker script for both standard images and XIP images.
+ */
+
+#include <autoconf.h>
+
+#include <arch/arm/cortex_m/scripts/linker.ld>

arch/arm/soc/nxp_lpc/lpc54xxx/soc.c

@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2017, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for nxp_lpc54114 platform
+ *
+ * This module provides routines to initialize and support board-level
+ * hardware for the nxp_lpc54114 platform.
+ */
+
+#include <kernel.h>
+#include <device.h>
+#include <init.h>
+#include <soc.h>
+#include <uart.h>
+#include <linker/sections.h>
+#include <arch/cpu.h>
+#include <cortex_m/exc.h>
+#include <clock_config.h>
+#include <fsl_lpc_power.h>
+#include <fsl_clock.h>
+#include <fsl_common.h>
+#include <fsl_device_registers.h>
+
+/**
+ *
+ * @brief Initialize the system clock
+ *
+ * @return N/A
+ *
+ */
+
+static ALWAYS_INLINE void clkInit(void)
+{
+	/* Set up the clock sources */
+
+	/* Ensure FRO is on */
+	POWER_DisablePD(kPDRUNCFG_PD_FRO_EN);
+
+	/*
+	 * Switch to FRO 12MHz first to ensure we can change voltage without
+	 * accidentally being below the voltage for current speed.
+	 */
+	CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
+
+	/* Set FLASH wait states for core */
+	CLOCK_SetFLASHAccessCyclesForFreq(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
+
+	/* Set up high frequency FRO output to selected frequency */
+	CLOCK_SetupFROClocking(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
+
+	/* Set up dividers */
+	/* Set AHBCLKDIV divider to value 1 */
+	CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);
+
+	/* Set up clock selectors - Attach clocks to the peripheries */
+	/* Switch MAIN_CLK to FRO_HF */
+	CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);
+
+	/* Attach 12 MHz clock to FLEXCOMM0 */
+	CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);
+}
+
+/**
+ *
+ * @brief Perform basic hardware initialization
+ *
+ * Initialize the interrupt controller device drivers.
+ * Also initialize the timer device driver, if required.
+ *
+ * @return 0
+ */
+
+static int nxp_lpc54114_init(struct device *arg)
+{
+	ARG_UNUSED(arg);
+
+	/* old interrupt lock level */
+	int oldLevel;
+
+	/* disable interrupts */
+	oldLevel = irq_lock();
+
+	_ClearFaults();
+
+	/* Initialize FRO/system clock to 48 MHz */
+	clkInit();
+
+	/*
+	 * install default handler that simply resets the CPU if configured in
+	 * the kernel, NOP otherwise
+	 */
+	NMI_INIT();
+
+	/* restore interrupt state */
+	irq_unlock(oldLevel);
+
+	return 0;
+}
+
+SYS_INIT(nxp_lpc54114_init, PRE_KERNEL_1, 0);

arch/arm/soc/nxp_lpc/lpc54xxx/soc.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2017, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Board configuration macros for the nxp_lpc54114 platform
+ *
+ * This header file is used to specify and describe board-level aspects for the
+ * 'nxp_lpc54114' platform.
+ */
+
+#ifndef _SOC__H_
+#define _SOC__H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef _ASMLANGUAGE
+#include <device.h>
+#include <misc/util.h>
+#include <fsl_common.h>
+#endif /* !_ASMLANGUAGE */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SOC__H_ */

dts/arm/nxp/nxp_lpc54xxx.dtsi

@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2017, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+
+/ {
+	cpus {
+		cpu@0 {
+			compatible = "arm,cortex-m4f";
+		};
+		cpu@1 {
+			compatible = "arm,cortex-m0+";
+		};
+	};
+
+	sram0:memory@20000000 {
+		compatible = "mmio-sram";
+		reg = <0x20000000 0x10000>;
+	};
+
+	sram1:memory@20010000 {
+		compatible = "mmio-sram";
+		reg = <0x20010000 0x10000>;
+	};
+
+	sram2:memory@20020000 {
+		compatible = "mmio-sram";
+		reg = <0x20020000 0x8000>;
+	};
+
+	sramx:memory@40000000{
+		compatible = "mmio-sram";
+		reg = <0x40000000 0x8000>;
+	};
+
+	soc {
+
+		flash0:flash@0 {
+			reg = <0 0x40000>;
+		};
+
+		usart0:usart@40086000 {
+			compatible = "nxp,lpc-usart";
+			reg = <0x40086000 0xE44>;
+			interrupts = <14 0>;
+			label = "USART_0";
+			status = "disabled";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};