cc3200: Make use of mem.h file in soc dtsi file.
This in preparation for adding a cc3220sf DTS file, which has a different address for sram0 than the cc3200. Also moved baud-rate out of soc dtsi file to board dts. Jira: JEP-1958 Change-Id: I641452c0a8a6d1ad4424e132d6ef2de71d8545b4 Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
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3 changed files with 21 additions and 7 deletions
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@ -1,10 +1,10 @@
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/dts-v1/;
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#include <ti/cc32xx_launchxl.dtsi>
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#include <ti/cc32xx.dtsi>
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/ {
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model = "TI CC3200 LaunchXL";
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compatible = "ti,cc32xx";
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compatible = "ti,cc3200-launchxl","ti,cc3200","ti,cc32xx";
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aliases {
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uart_0 = &uart0;
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@ -19,4 +19,5 @@
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&uart0 {
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status = "ok";
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baud-rate = <115200>;
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};
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@ -1,7 +1,8 @@
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#include <arm/armv7-m.dtsi>
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#include <inc/hw_ints.h>
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#include <ti/mem.h>
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/* Note: Zephyr uses exception numbers, vs the IRQ #s used by the CC3200 SDK */
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/* Note: Zephyr uses exception numbers, vs the IRQ #s used by the CC32XX SDK */
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/* which are offset by 16: */
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#define EXP_UARTA0 (INT_UARTA0 - 16)
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#define EXP_UARTA1 (INT_UARTA1 - 16)
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@ -15,12 +16,12 @@
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sram0: memory {
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compatible = "sram";
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reg = <0x20004000 0x3C000>;
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reg = <DT_SRAM_START DT_SRAM_SIZE>;
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};
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flash0: serial-flash {
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compatible = "serial-flash";
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reg = <0x0 0x80000>;
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reg = <0x0 DT_SFLASH_SIZE>;
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};
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soc {
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@ -28,7 +29,6 @@
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compatible = "ti,cc32xx-uart";
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reg = <0x4000C000 0x4c>;
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interrupts = <EXP_UARTA0 3>;
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baud-rate = <115200>;
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status = "disabled";
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};
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@ -36,7 +36,6 @@
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compatible = "ti,cc32xx-uart";
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reg = <0x4000D000 0x4c>;
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interrupts = <EXP_UARTA1 3>;
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baud-rate = <115200>;
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status = "disabled";
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};
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14
dts/arm/ti/mem.h
Normal file
14
dts/arm/ti/mem.h
Normal file
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@ -0,0 +1,14 @@
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#ifndef __DT_BINDING_TI_MEM_H
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#define __DT_BINDING_TI_MEM_H
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#define __SIZE_K(x) (x * 1024)
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#if defined(CONFIG_SOC_CC3200)
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#define DT_SFLASH_SIZE __SIZE_K(1024)
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#define DT_SRAM_SIZE __SIZE_K(240)
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#define DT_SRAM_START 0x20004000
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#else
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#error "Flash and RAM sizes not defined for this chip"
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#endif
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#endif /* __DT_BINDING_TI_MEM_H */
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