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arm: stm32f4: Add CAN1 support

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Add CAN1 pinmux definitions and DT entries for STM32F4 series.

Signed-off-by: Erwin Rol <erwin@erwinrol.com>
This commit is contained in:
Erwin Rol 2019-01-19 11:30:40 +01:00 • committed by Kumar Gala
commit efa44b1885
3 changed files with 52 additions and 0 deletions
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19
drivers/pinmux/stm32/pinmux_stm32f4.h
View file

@ -111,6 +111,8 @@
(STM32_PINMUX_ALT_FUNC_7 | STM32_OPENDRAIN_PULLUP)
#define STM32F4_PINMUX_FUNC_PA11_USART6_TX \
(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_PULLUP)
#define STM32F4_PINMUX_FUNC_PA11_CAN1_RX \
(STM32_PINMUX_ALT_FUNC_9 | STM32_PUSHPULL_PULLUP)
#define STM32F4_PINMUX_FUNC_PA11_UART4_RX \
(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL)
#define STM32F4_PINMUX_FUNC_PA11_OTG_FS_DM \
@ -120,6 +122,8 @@
(STM32_PINMUX_ALT_FUNC_7 | STM32_OPENDRAIN_PULLUP)
#define STM32F4_PINMUX_FUNC_PA12_USART6_RX \
(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_NOPULL)
#define STM32F4_PINMUX_FUNC_PA12_CAN1_TX \
(STM32_PINMUX_ALT_FUNC_9 | STM32_PUSHPULL_NOPULL)
#define STM32F4_PINMUX_FUNC_PA12_UART4_TX \
(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_PULLUP)
#define STM32F4_PINMUX_FUNC_PA12_OTG_FS_DP \
@ -201,6 +205,8 @@
(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
#define STM32F4_PINMUX_FUNC_PB8_I2S5_SD \
(STM32_PINMUX_ALT_FUNC_6 | STM32_PUSHPULL_NOPULL)
#define STM32F4_PINMUX_FUNC_PB8_CAN1_RX \
(STM32_PINMUX_ALT_FUNC_9 | STM32_PUSHPULL_PULLUP)
#define STM32F4_PINMUX_FUNC_PB8_UART5_RX \
(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL)
#define STM32F4_PINMUX_FUNC_PB8_ETH \
@ -213,6 +219,8 @@
(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
#define STM32F4_PINMUX_FUNC_PB9_I2C2_SDA \
(STM32_PINMUX_ALT_FUNC_9 | STM32_OPENDRAIN_PULLUP)
#define STM32F4_PINMUX_FUNC_PB9_CAN1_TX \
(STM32_PINMUX_ALT_FUNC_9 | STM32_PUSHPULL_NOPULL)
#define STM32F4_PINMUX_FUNC_PB9_UART5_TX \
(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_PULLUP)
#define STM32F4_PINMUX_FUNC_PB9_SPI2_NSS \
@ -359,9 +367,14 @@
(STM32_PINMUX_ALT_FUNC_4 | STM32_PUSHPULL_PULLUP)
/* Port D */
#define STM32F4_PINMUX_FUNC_PD0_CAN1_RX \
(STM32_PINMUX_ALT_FUNC_9 | STM32_PUSHPULL_PULLUP)
#define STM32F4_PINMUX_FUNC_PD0_UART4_RX \
(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL)
#define STM32F4_PINMUX_FUNC_PD1_CAN1_TX \
(STM32_PINMUX_ALT_FUNC_9 | STM32_PUSHPULL_NOPULL)
#define STM32F4_PINMUX_FUNC_PD2_UART5_RX \
(STM32_PINMUX_ALT_FUNC_8 | STM32_PUSHPULL_NOPULL)
@ -551,7 +564,13 @@
#define STM32F4_PINMUX_FUNC_PH8_I2C3_SDA \
(STM32_PINMUX_ALT_FUNC_4 | STM32_OPENDRAIN_PULLUP)
#define STM32F4_PINMUX_FUNC_PH13_CAN1_TX \
(STM32_PINMUX_ALT_FUNC_9 | STM32_PUSHPULL_NOPULL)
/* Port I */
#define STM32F4_PINMUX_FUNC_PI9_CAN1_RX \
(STM32_PINMUX_ALT_FUNC_9 | STM32_PUSHPULL_PULLUP)
#define STM32F4_PINMUX_FUNC_PI10_ETH \
(STM32_PINMUX_ALT_FUNC_11 | STM32_PUSHPULL_NOPULL | \
STM32_OSPEEDR_VERY_HIGH_SPEED)

18
dts/arm/st/f4/stm32f405.dtsi
View file

@ -176,6 +176,24 @@
status = "disabled";
label= "OTGHS";
};
can1: can@40006400 {
compatible = "st,stm32-can";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40006400 0x400>;
interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
interrupt-names = "TX", "RX0", "RX1", "SCE";
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
status = "disabled";
label = "CAN_1";
bus-speed = <125000>;
sjw = <1>;
prop-seg = <0>;
phase-seg1 = <5>;
phase-seg2 = <6>;
};
};
otghs_fs_phy: otghs_fs_phy {

15
soc/arm/st_stm32/stm32f4/dts_fixup.h
View file

@ -412,4 +412,19 @@
#define DT_ADC_1_CLOCK_BITS DT_ST_STM32_ADC_40012000_CLOCK_BITS_0
#define DT_ADC_1_CLOCK_BUS DT_ST_STM32_ADC_40012000_CLOCK_BUS_0
#define DT_CAN_1_BASE_ADDRESS DT_ST_STM32_CAN_40006400_BASE_ADDRESS
#define DT_CAN_1_BUS_SPEED DT_ST_STM32_CAN_40006400_BUS_SPEED
#define DT_CAN_1_NAME DT_ST_STM32_CAN_40006400_LABEL
#define DT_CAN_1_IRQ_TX DT_ST_STM32_CAN_40006400_IRQ_TX
#define DT_CAN_1_IRQ_RX0 DT_ST_STM32_CAN_40006400_IRQ_RX0
#define DT_CAN_1_IRQ_RX1 DT_ST_STM32_CAN_40006400_IRQ_RX1
#define DT_CAN_1_IRQ_SCE DT_ST_STM32_CAN_40006400_IRQ_SCE
#define DT_CAN_1_IRQ_PRIORITY DT_ST_STM32_CAN_40006400_IRQ_0_PRIORITY
#define DT_CAN_1_SJW DT_ST_STM32_CAN_40006400_SJW
#define DT_CAN_1_PROP_SEG DT_ST_STM32_CAN_40006400_PROP_SEG
#define DT_CAN_1_PHASE_SEG1 DT_ST_STM32_CAN_40006400_PHASE_SEG1
#define DT_CAN_1_PHASE_SEG2 DT_ST_STM32_CAN_40006400_PHASE_SEG2
#define DT_CAN_1_CLOCK_BUS DT_ST_STM32_CAN_40006400_CLOCK_BUS
#define DT_CAN_1_CLOCK_BITS DT_ST_STM32_CAN_40006400_CLOCK_BITS
/* End of SoC Level DTS fixup file */