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drivers: counter: Add SAM0 basic counter support

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This adds support for the basic timer counter (TC) found on SAM0
series parts.  This driver only supports running the counter
in 32 bit wide mode.  Since this mode explicitly slaves the odd
counters to the even ones, only instances of the even ones are
defined.

Tested with tests/drivers/counter/counter_basic_api on SAMD21.

Signed-off-by: Derek Hageman <hageman@inthat.cloud>
This commit is contained in:
Derek Hageman 2019-04-01 19:15:03 -06:00 • committed by Anas Nashif
commit a4f3e628e5
13 changed files with 632 additions and 0 deletions
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1
drivers/counter/CMakeLists.txt
View file

@ -12,5 +12,6 @@ zephyr_library_sources_ifdef(CONFIG_COUNTER_NRF_TIMER counter_nrfx_tim
zephyr_library_sources_ifdef(CONFIG_COUNTER_NRF_RTC counter_nrfx_rtc.c)
zephyr_library_sources_ifdef(CONFIG_RTC_QMSI counter_rtc_qmsi.c)
zephyr_library_sources_ifdef(CONFIG_COUNTER_RTC_STM32 counter_ll_stm32_rtc.c)
zephyr_library_sources_ifdef(CONFIG_COUNTER_SAM0_TC32 counter_sam0_tc32.c)
zephyr_library_sources_ifdef(CONFIG_USERSPACE counter_handlers.c)

2
drivers/counter/Kconfig
View file

@ -34,4 +34,6 @@ source "drivers/counter/Kconfig.imx_epit"
source "drivers/counter/Kconfig.stm32_rtc"
source "drivers/counter/Kconfig.sam0"
endif # COUNTER

28
drivers/counter/Kconfig.sam0 Normal file
View file

@ -0,0 +1,28 @@
# Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
#
# SPDX-License-Identifier: Apache-2.0
#
menuconfig COUNTER_SAM0_TC32
bool "SAM0 series 32-bit basic timer driver"
default y
depends on SOC_FAMILY_SAM0
help
Enable the SAM0 series timer counter (TC) driver in 32-bit wide
mode.
if COUNTER_SAM0_TC32
index = 0
source "drivers/counter/Kconfig.template.sam0_tc32"
index = 2
source "drivers/counter/Kconfig.template.sam0_tc32"
index = 4
source "drivers/counter/Kconfig.template.sam0_tc32"
index = 6
source "drivers/counter/Kconfig.template.sam0_tc32"
endif # COUNTER_SAM0_TC32

38
drivers/counter/Kconfig.template.sam0_tc32 Normal file
View file

@ -0,0 +1,38 @@
# Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
#
# SPDX-License-Identifier: Apache-2.0
#
choice
bool "Timer $(index) prescaler"
config COUNTER_SAM0_TC32_$(index)_PRESCALER_1
bool "clock / 1"
config COUNTER_SAM0_TC32_$(index)_PRESCALER_2
bool "clock / 2"
config COUNTER_SAM0_TC32_$(index)_PRESCALER_4
bool "clock / 4"
config COUNTER_SAM0_TC32_$(index)_PRESCALER_8
bool "clock / 8"
config COUNTER_SAM0_TC32_$(index)_PRESCALER_16
bool "clock / 16"
config COUNTER_SAM0_TC32_$(index)_PRESCALER_64
bool "clock / 64"
config COUNTER_SAM0_TC32_$(index)_PRESCALER_256
bool "clock / 256"
config COUNTER_SAM0_TC32_$(index)_PRESCALER_1024
bool "clock / 1024"
endchoice
config COUNTER_SAM0_TC32_$(index)_DIVISOR
int
default 1 if COUNTER_SAM0_TC32_$(index)_PRESCALER_1
default 2 if COUNTER_SAM0_TC32_$(index)_PRESCALER_2
default 4 if COUNTER_SAM0_TC32_$(index)_PRESCALER_4
default 8 if COUNTER_SAM0_TC32_$(index)_PRESCALER_8
default 16 if COUNTER_SAM0_TC32_$(index)_PRESCALER_16
default 64 if COUNTER_SAM0_TC32_$(index)_PRESCALER_64
default 256 if COUNTER_SAM0_TC32_$(index)_PRESCALER_256
default 1024 if COUNTER_SAM0_TC32_$(index)_PRESCALER_1024

457
drivers/counter/counter_sam0_tc32.c Normal file
View file

@ -0,0 +1,457 @@
/*
* Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <counter.h>
#include <device.h>
#include <soc.h>
#include <logging/log.h>
LOG_MODULE_REGISTER(counter_sam0_tc32, CONFIG_COUNTER_LOG_LEVEL);
struct counter_sam0_tc32_ch_data {
counter_alarm_callback_t callback;
void *user_data;
};
struct counter_sam0_tc32_data {
counter_top_callback_t top_cb;
void *top_user_data;
struct counter_sam0_tc32_ch_data ch;
};
struct counter_sam0_tc32_config {
struct counter_config_info info;
TcCount32 *regs;
#ifdef MCLK
volatile u32_t *mclk;
u32_t mclk_mask;
u16_t gclk_id;
#else
u32_t pm_apbcmask;
u16_t gclk_clkctrl_id;
#endif
u16_t prescaler;
void (*irq_config_func)(struct device *dev);
};
#define DEV_CFG(dev) ((const struct counter_sam0_tc32_config *const) \
(dev)->config->config_info)
#define DEV_DATA(dev) ((struct counter_sam0_tc32_data *const) \
(dev)->driver_data)
static void wait_synchronization(TcCount32 *regs)
{
#if defined(TC_SYNCBUSY_MASK)
/* SYNCBUSY is a register */
while ((regs->SYNCBUSY.reg & TC_SYNCBUSY_MASK) != 0) {
}
#elif defined(TC_STATUS_SYNCBUSY)
/* SYNCBUSY is a bit */
while ((regs->STATUS.reg & TC_STATUS_SYNCBUSY) != 0) {
}
#else
#error Unsupported device
#endif
}
static void read_synchronize_count(TcCount32 *regs)
{
#if defined(TC_READREQ_RREQ)
regs->READREQ.reg = TC_READREQ_RREQ |
TC_READREQ_ADDR(TC_COUNT32_COUNT_OFFSET);
wait_synchronization(regs);
#elif defined(TC_CTRLBSET_CMD_READSYNC)
regs->CTRLBSET.reg = TC_CTRLBSET_CMD_READSYNC;
wait_synchronization(regs);
#else
ARG_UNUSED(regs);
#endif
}
static int counter_sam0_tc32_start(struct device *dev)
{
const struct counter_sam0_tc32_config *const cfg = DEV_CFG(dev);
TcCount32 *tc = cfg->regs;
/*
* This will also reset the current counter value if it's
* already running.
*/
tc->CTRLBSET.reg = TC_CTRLBSET_CMD_RETRIGGER;
wait_synchronization(tc);
return 0;
}
static int counter_sam0_tc32_stop(struct device *dev)
{
const struct counter_sam0_tc32_config *const cfg = DEV_CFG(dev);
TcCount32 *tc = cfg->regs;
/*
* The older (pre SAML1x) manuals claim the counter retains its
* value on stop, but this doesn't actually seem to happen.
* The SAML1x manual says it resets, which is what the SAMD21
* counter actually appears to do.
*/
tc->CTRLBSET.reg = TC_CTRLBSET_CMD_STOP;
wait_synchronization(tc);
return 0;
}
static u32_t counter_sam0_tc32_read(struct device *dev)
{
const struct counter_sam0_tc32_config *const cfg = DEV_CFG(dev);
TcCount32 *tc = cfg->regs;
read_synchronize_count(tc);
return tc->COUNT.reg;
}
static void counter_sam0_tc32_relative_alarm(struct device *dev, u32_t ticks)
{
struct counter_sam0_tc32_data *data = DEV_DATA(dev);
const struct counter_sam0_tc32_config *const cfg = DEV_CFG(dev);
TcCount32 *tc = cfg->regs;
u32_t before;
u32_t target;
u32_t after;
u32_t max;
read_synchronize_count(tc);
before = tc->COUNT.reg;
target = before + ticks;
max = tc->CC[0].reg;
if (target > max) {
target -= max;
}
tc->CC[1].reg = target;
wait_synchronization(tc);
tc->INTFLAG.reg = TC_INTFLAG_MC1;
read_synchronize_count(tc);
after = tc->COUNT.reg;
/* Pending now, so no further checking required */
if (tc->INTFLAG.bit.MC1) {
goto out_future;
}
/*
* Check if we missed the interrupt and call the handler
* immediately if we did.
*/
if (after < target) {
goto out_future;
}
/* Check wrapped */
if (target < before && after >= before) {
goto out_future;
}
counter_alarm_callback_t cb = data->ch.callback;
tc->INTENCLR.reg = TC_INTENCLR_MC1;
tc->INTFLAG.reg = TC_INTFLAG_MC1;
data->ch.callback = NULL;
cb(dev, 0, target, data->ch.user_data);
return;
out_future:
tc->INTENSET.reg = TC_INTFLAG_MC1;
}
static int counter_sam0_tc32_set_alarm(struct device *dev, u8_t chan_id,
const struct counter_alarm_cfg *alarm_cfg)
{
struct counter_sam0_tc32_data *data = DEV_DATA(dev);
const struct counter_sam0_tc32_config *const cfg = DEV_CFG(dev);
TcCount32 *tc = cfg->regs;
ARG_UNUSED(chan_id);
if (alarm_cfg->ticks > tc->CC[0].reg) {
return -EINVAL;
}
int key = irq_lock();
if (data->ch.callback) {
irq_unlock(key);
return -EBUSY;
}
data->ch.callback = alarm_cfg->callback;
data->ch.user_data = alarm_cfg->user_data;
if (alarm_cfg->absolute) {
tc->CC[1].reg = alarm_cfg->ticks;
wait_synchronization(tc);
tc->INTFLAG.reg = TC_INTFLAG_MC1;
tc->INTENSET.reg = TC_INTFLAG_MC1;
} else {
counter_sam0_tc32_relative_alarm(dev, alarm_cfg->ticks);
}
irq_unlock(key);
return 0;
}
static int counter_sam0_tc32_cancel_alarm(struct device *dev, u8_t chan_id)
{
struct counter_sam0_tc32_data *data = DEV_DATA(dev);
const struct counter_sam0_tc32_config *const cfg = DEV_CFG(dev);
TcCount32 *tc = cfg->regs;
int key = irq_lock();
ARG_UNUSED(chan_id);
data->ch.callback = NULL;
tc->INTENCLR.reg = TC_INTENCLR_MC1;
tc->INTFLAG.reg = TC_INTFLAG_MC1;
irq_unlock(key);
return 0;
}
static int counter_sam0_tc32_set_top_value(struct device *dev, u32_t ticks,
counter_top_callback_t callback,
void *user_data)
{
bool reset = true;
struct counter_sam0_tc32_data *data = DEV_DATA(dev);
const struct counter_sam0_tc32_config *const cfg = DEV_CFG(dev);
TcCount32 *tc = cfg->regs;
int key = irq_lock();
if (data->ch.callback) {
irq_unlock(key);
return -EBUSY;
}
if (callback) {
data->top_cb = callback;
data->top_user_data = user_data;
tc->INTENSET.reg = TC_INTFLAG_MC0;
} else {
tc->INTENCLR.reg = TC_INTFLAG_MC0;
}
tc->CC[0].reg = ticks;
if (reset) {
tc->CTRLBSET.reg = TC_CTRLBSET_CMD_RETRIGGER;
} else {
/*
* Top trigger is on equality of the rising edge only, so
* manually reset it if the counter has missed the new top.
*/
if (counter_sam0_tc32_read(dev) >= ticks) {
tc->CTRLBSET.reg = TC_CTRLBSET_CMD_RETRIGGER;
}
}
wait_synchronization(tc);
tc->INTFLAG.reg = TC_INTFLAG_MC0;
irq_unlock(key);
return 0;
}
static u32_t counter_sam0_tc32_get_pending_int(struct device *dev)
{
const struct counter_sam0_tc32_config *const cfg = DEV_CFG(dev);
TcCount32 *tc = cfg->regs;
return tc->INTFLAG.reg & (TC_INTFLAG_MC0 | TC_INTFLAG_MC1);
}
static u32_t counter_sam0_tc32_get_top_value(struct device *dev)
{
const struct counter_sam0_tc32_config *const cfg = DEV_CFG(dev);
TcCount32 *tc = cfg->regs;
/*
* Unsync read is safe here because we're not using
* capture mode, so things are only set from the CPU
* end.
*/
return tc->CC[0].reg;
}
static u32_t counter_sam0_tc32_get_max_relative_alarm(struct device *dev)
{
return counter_sam0_tc32_get_top_value(dev) - 1;
}
static void counter_sam0_tc32_isr(void *arg)
{
struct device *dev = (struct device *)arg;
struct counter_sam0_tc32_data *data = DEV_DATA(dev);
const struct counter_sam0_tc32_config *const cfg = DEV_CFG(dev);
TcCount32 *tc = cfg->regs;
u8_t status = tc->INTFLAG.reg;
/* Acknowledge all interrupts */
tc->INTFLAG.reg = status;
if (status & TC_INTFLAG_MC1) {
if (data->ch.callback) {
counter_alarm_callback_t cb = data->ch.callback;
tc->INTENCLR.reg = TC_INTENCLR_MC1;
data->ch.callback = NULL;
cb(dev, 0, tc->CC[1].reg, data->ch.user_data);
}
}
if (status & TC_INTFLAG_MC0) {
if (data->top_cb) {
data->top_cb(dev, data->top_user_data);
}
}
}
static int counter_sam0_tc32_initialize(struct device *dev)
{
const struct counter_sam0_tc32_config *const cfg = DEV_CFG(dev);
TcCount32 *tc = cfg->regs;
#ifdef MCLK
/* Enable the GCLK */
GCLK->PCHCTRL[cfg->gclk_id].reg = GCLK_PCHCTRL_GEN_GCLK0 |
GCLK_PCHCTRL_CHEN;
/* Enable TC clock in MCLK */
*cfg->mclk |= cfg->mclk_mask;
#else
/* Enable the GCLK */
GCLK->CLKCTRL.reg = cfg->gclk_clkctrl_id | GCLK_CLKCTRL_GEN_GCLK0 |
GCLK_CLKCTRL_CLKEN;
/* Enable clock in PM */
PM->APBCMASK.reg |= cfg->pm_apbcmask;
#endif
/*
* In 32 bit mode, NFRQ mode always uses MAX as the counter top, so
* use MFRQ mode which uses CC0 as the top at the expense of only
* having CC1 available for alarms.
*/
tc->CTRLA.reg = TC_CTRLA_MODE_COUNT32 |
#ifdef TC_CTRLA_WAVEGEN_MFRQ
TC_CTRLA_WAVEGEN_MFRQ |
#endif
cfg->prescaler;
wait_synchronization(tc);
#ifdef TC_WAVE_WAVEGEN_MFRQ
tc->WAVE.reg = TC_WAVE_WAVEGEN_MFRQ;
#endif
/* Disable all interrupts */
tc->INTENCLR.reg = TC_INTENCLR_MASK;
/* Set the initial top as the maximum */
tc->CC[0].reg = UINT32_MAX;
cfg->irq_config_func(dev);
tc->CTRLA.bit.ENABLE = 1;
wait_synchronization(tc);
/* Stop the counter initially */
tc->CTRLBSET.reg = TC_CTRLBSET_CMD_STOP;
wait_synchronization(tc);
return 0;
}
static const struct counter_driver_api counter_sam0_tc32_driver_api = {
.start = counter_sam0_tc32_start,
.stop = counter_sam0_tc32_stop,
.read = counter_sam0_tc32_read,
.set_alarm = counter_sam0_tc32_set_alarm,
.cancel_alarm = counter_sam0_tc32_cancel_alarm,
.set_top_value = counter_sam0_tc32_set_top_value,
.get_pending_int = counter_sam0_tc32_get_pending_int,
.get_top_value = counter_sam0_tc32_get_top_value,
.get_max_relative_alarm = counter_sam0_tc32_get_max_relative_alarm,
};
#ifdef MCLK
#define COUNTER_SAM0_TC32_CLOCK_CONTROL(n) \
.mclk = MCLK_TC##n, \
.mclk_mask = MCLK_TC##n##_MASK, \
.gclk_id = TC##n##_GCLK_ID,
#else
#define COUNTER_SAM0_TC32_CLOCK_CONTROL(n) \
.pm_apbcmask = PM_APBCMASK_TC##n, \
.gclk_clkctrl_id = UTIL_CAT(GCLK_CLKCTRL_ID_TC ## n ## _TC, \
UTIL_INC(n)),
#endif
#define COUNTER_SAM0_TC32_DEVICE(n) \
static void counter_sam0_tc32_config_##n(struct device *dev); \
static const struct counter_sam0_tc32_config \
counter_sam0_tc32_dev_config_##n = { \
.info = { \
.max_top_value = UINT32_MAX, \
.freq = SOC_ATMEL_SAM0_GCLK0_FREQ_HZ / \
CONFIG_COUNTER_SAM0_TC32_##n##_DIVISOR, \
.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
.channels = 1 \
}, \
.regs = (TcCount32 *)DT_ATMEL_SAM0_TC32_TC_##n##_BASE_ADDRESS,\
COUNTER_SAM0_TC32_CLOCK_CONTROL(n) \
.prescaler = UTIL_CAT(TC_CTRLA_PRESCALER_DIV, \
CONFIG_COUNTER_SAM0_TC32_##n##_DIVISOR), \
.irq_config_func = &counter_sam0_tc32_config_##n, \
}; \
static struct counter_sam0_tc32_data counter_sam0_tc32_dev_data_##n; \
DEVICE_AND_API_INIT(counter_sam0_tc32_##n, \
DT_ATMEL_SAM0_TC32_TC_##n##_LABEL, \
&counter_sam0_tc32_initialize, \
&counter_sam0_tc32_dev_data_##n, \
&counter_sam0_tc32_dev_config_##n, PRE_KERNEL_1, \
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
&counter_sam0_tc32_driver_api); \
static void counter_sam0_tc32_config_##n(struct device *dev) \
{ \
IRQ_CONNECT(DT_ATMEL_SAM0_TC32_TC_##n##_IRQ, \
DT_ATMEL_SAM0_TC32_TC_##n##_IRQ_PRIORITY, \
counter_sam0_tc32_isr, \
DEVICE_GET(counter_sam0_tc32_##n), \
0); \
irq_enable(DT_ATMEL_SAM0_TC32_TC_##n##_IRQ); \
}
#if DT_ATMEL_SAM0_TC32_TC_0_BASE_ADDRESS
COUNTER_SAM0_TC32_DEVICE(0);
#endif
#if DT_ATMEL_SAM0_TC32_TC_2_BASE_ADDRESS
COUNTER_SAM0_TC32_DEVICE(2);
#endif
#if DT_ATMEL_SAM0_TC32_TC_4_BASE_ADDRESS
COUNTER_SAM0_TC32_DEVICE(4);
#endif
#if DT_ATMEL_SAM0_TC32_TC_6_BASE_ADDRESS
COUNTER_SAM0_TC32_DEVICE(6);
#endif

8
dts/arm/atmel/samd.dtsi
View file

@ -47,6 +47,8 @@
sercom-3 = &sercom3;
sercom-4 = &sercom4;
sercom-5 = &sercom5;
tc-4 = &tc4;
};
soc {
@ -135,6 +137,12 @@
label = "SERCOM5";
};
tc4: tc@42003000 {
compatible = "atmel,sam0-tc32";
reg = <0x42003000 0x20>;
label = "TIMER_4";
};
porta: gpio@41004400 {
compatible = "atmel,sam0-gpio";
reg = <0x41004400 0x80>;

35
dts/arm/atmel/samd20.dtsi
View file

@ -6,6 +6,37 @@
#include <atmel/samd.dtsi>
/ {
aliases {
tc-0 = &tc0;
tc-2 = &tc2;
tc-6 = &tc6;
};
soc {
tc0: tc@42002000 {
compatible = "atmel,sam0-tc32";
reg = <0x42002000 0x20>;
interrupts = <13 0>;
label = "TIMER_0";
};
tc2: tc@42002800 {
compatible = "atmel,sam0-tc32";
reg = <0x42002800 0x20>;
interrupts = <15 0>;
label = "TIMER_2";
};
tc6: tc@42003800 {
compatible = "atmel,sam0-tc32";
reg = <0x42003800 0x20>;
interrupts = <19 0>;
label = "TIMER_6";
};
};
};
&sercom0 {
interrupts = <7 0>;
};
@ -30,6 +61,10 @@
interrupts = <12 0>;
};
&tc4 {
interrupts = <17 0>;
};
&adc {
interrupts = <21 0>;
};

15
dts/arm/atmel/samd21.dtsi
View file

@ -7,6 +7,10 @@
#include <atmel/samd.dtsi>
/ {
aliases {
tc-6 = &tc6;
};
soc {
usb0: usb@41005000 {
compatible = "atmel,sam0-usb";
@ -23,6 +27,13 @@
interrupts = <6 0>;
label = "DMA_0";
};
tc6: tc@42003800 {
compatible = "atmel,sam0-tc32";
reg = <0x42003800 0x20>;
interrupts = <21 0>;
label = "TIMER_6";
};
};
};
@ -50,6 +61,10 @@
interrupts = <14 0>;
};
&tc4 {
interrupts = <19 0>;
};
&adc {
interrupts = <23 0>;
};

4
dts/arm/atmel/samr21.dtsi
View file

@ -69,6 +69,10 @@
interrupts = <14 0>;
};
&tc4 {
interrupts = <19 0>;
};
&adc {
interrupts = <23 0>;
};

38
dts/bindings/timer/atmel,sam0-tc32.yaml Normal file
View file

@ -0,0 +1,38 @@
#
# Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
#
# SPDX-License-Identifier: Apache-2.0
#
---
title: Atmel SAM0 32-bit Basic Timer
version: 0.1
description: >
This binding gives a base representation of the Atmel SAM0 timer
counter (TC) operating in 32-bit wide mode.
properties:
compatible:
type: string
category: required
description: compatible strings
constraint: "atmel,sam0-tc32"
reg:
type: array
category: required
description: mmio register space
generation: define
interrupts:
type: array
category: required
description: required interrupts
generation: define
label:
type: string
category: required
description: Human readable string describing the device (used by Zephyr for API name)
generation: define
...

2
soc/arm/atmel_sam0/samd20/dts_fixup.h
View file

@ -6,6 +6,8 @@
#define CONFIG_WDT_0_NAME DT_ATMEL_SAM0_WATCHDOG_0_LABEL
#define CONFIG_COUNTER_0_NAME DT_ATMEL_SAM0_TC32_0_LABEL
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
/* End of SoC Level DTS fixup file */

2
soc/arm/atmel_sam0/samd21/dts_fixup.h
View file

@ -6,6 +6,8 @@
#define CONFIG_WDT_0_NAME DT_ATMEL_SAM0_WATCHDOG_0_LABEL
#define CONFIG_COUNTER_0_NAME DT_ATMEL_SAM0_TC32_0_LABEL
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
/* End of SoC Level DTS fixup file */

2
soc/arm/atmel_sam0/samr21/dts_fixup.h
View file

@ -10,6 +10,8 @@
#define CONFIG_WDT_0_NAME DT_ATMEL_SAM0_WATCHDOG_0_LABEL
#define CONFIG_COUNTER_0_NAME DT_ATMEL_SAM0_TC32_0_LABEL
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
/* End of SoC Level DTS fixup file */