dts/arm/st_stm32: Add SPI nodes to STM32 F7 series
This patch adds SPI nodes to STM32 F7 series, as well as the corresponding dts fixup entries. Signed-off-by: Christian Taedcke <hacking@taedcke.com>
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2 changed files with 96 additions and 0 deletions
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@ -241,6 +241,72 @@
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label = "I2C_3";
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};
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spi1: spi@40013000 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
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interrupts = <35 5>;
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status = "disabled";
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label = "SPI_1";
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};
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spi2: spi@40003800 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
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interrupts = <36 5>;
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status = "disabled";
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label = "SPI_2";
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};
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spi3: spi@40003C00 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003C00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
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interrupts = <51 5>;
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status = "disabled";
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label = "SPI_3";
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};
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spi4: spi@40013400 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
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interrupts = <84 5>;
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status = "disabled";
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label = "SPI_4";
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};
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spi5: spi@40015000 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40015000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
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interrupts = <85 5>;
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status = "disabled";
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label = "SPI_5";
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};
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spi6: spi@40015400 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40015400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
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interrupts = <86 5>;
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status = "disabled";
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label = "SPI_6";
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};
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timers1: timers@40010000 {
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compatible = "st,stm32-timers";
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reg = <0x40010000 0x400>;
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@ -74,6 +74,36 @@
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#define CONFIG_I2C_3_ERROR_IRQ ST_STM32_I2C_V2_40005C00_IRQ_ERROR
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#define CONFIG_I2C_3_BITRATE ST_STM32_I2C_V2_40005C00_CLOCK_FREQUENCY
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#define CONFIG_SPI_1_BASE_ADDRESS ST_STM32_SPI_40013000_BASE_ADDRESS
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#define CONFIG_SPI_1_IRQ_PRI ST_STM32_SPI_40013000_IRQ_0_PRIORITY
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#define CONFIG_SPI_1_NAME ST_STM32_SPI_40013000_LABEL
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#define CONFIG_SPI_1_IRQ ST_STM32_SPI_40013000_IRQ_0
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#define CONFIG_SPI_2_BASE_ADDRESS ST_STM32_SPI_40003800_BASE_ADDRESS
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#define CONFIG_SPI_2_IRQ_PRI ST_STM32_SPI_40003800_IRQ_0_PRIORITY
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#define CONFIG_SPI_2_NAME ST_STM32_SPI_40003800_LABEL
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#define CONFIG_SPI_2_IRQ ST_STM32_SPI_40003800_IRQ_0
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#define CONFIG_SPI_3_BASE_ADDRESS ST_STM32_SPI_40003C00_BASE_ADDRESS
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#define CONFIG_SPI_3_IRQ_PRI ST_STM32_SPI_40003C00_IRQ_0_PRIORITY
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#define CONFIG_SPI_3_NAME ST_STM32_SPI_40003C00_LABEL
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#define CONFIG_SPI_3_IRQ ST_STM32_SPI_40003C00_IRQ_0
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#define CONFIG_SPI_4_BASE_ADDRESS ST_STM32_SPI_40013400_BASE_ADDRESS
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#define CONFIG_SPI_4_IRQ_PRI ST_STM32_SPI_40013400_IRQ_0_PRIORITY
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#define CONFIG_SPI_4_NAME ST_STM32_SPI_40013400_LABEL
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#define CONFIG_SPI_4_IRQ ST_STM32_SPI_40013400_IRQ_0
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#define CONFIG_SPI_5_BASE_ADDRESS ST_STM32_SPI_40015000_BASE_ADDRESS
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#define CONFIG_SPI_5_IRQ_PRI ST_STM32_SPI_40015000_IRQ_0_PRIORITY
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#define CONFIG_SPI_5_NAME ST_STM32_SPI_40015000_LABEL
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#define CONFIG_SPI_5_IRQ ST_STM32_SPI_40015000_IRQ_0
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#define CONFIG_SPI_6_BASE_ADDRESS ST_STM32_SPI_40015400_BASE_ADDRESS
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#define CONFIG_SPI_6_IRQ_PRI ST_STM32_SPI_40015400_IRQ_0_PRIORITY
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#define CONFIG_SPI_6_NAME ST_STM32_SPI_40015400_LABEL
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#define CONFIG_SPI_6_IRQ ST_STM32_SPI_40015400_IRQ_0
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#ifdef ST_STM32_OTGFS_50000000_BASE_ADDRESS
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#define CONFIG_USB_BASE_ADDRESS ST_STM32_OTGFS_50000000_BASE_ADDRESS
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#define CONFIG_USB_IRQ ST_STM32_OTGFS_50000000_IRQ_OTGFS
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