arm: stm32f2: Add support for stm32f2 series

Add necessary kconfig and DTS files for stm32f2 series

Signed-off-by: qianfan Zhao <qianfanguijin@163.com>

arch/arm/soc/st_stm32/stm32f2/CMakeLists.txt

@@ -0,0 +1,4 @@
+zephyr_include_directories(${ZEPHYR_BASE}/drivers)
+zephyr_sources(
+  soc.c
+  )

arch/arm/soc/st_stm32/stm32f2/Kconfig.defconfig.series

@@ -0,0 +1,15 @@
+# Kconfig - ST Microelectronics STM32F2 MCU line
+#
+# Copyright (c) 2018 qianfan Zhao <qianfanguijin@163.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_SERIES_STM32F2X
+
+gsource "arch/arm/soc/st_stm32/stm32f2/Kconfig.defconfig.stm32f2*"
+
+config SOC_SERIES
+	default "stm32f2"
+
+endif # SOC_SERIES_STM32F2X

arch/arm/soc/st_stm32/stm32f2/Kconfig.series

@@ -0,0 +1,17 @@
+# Kconfig - ST Microelectronics STM32F2X MCU series
+#
+# Copyright (c) 2018 qianfan Zhao <qianfanguijin@163.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_SERIES_STM32F2X
+	bool "stm32f2x Series MCU"
+	select CPU_CORTEX_M
+	select CPU_CORTEX_M3
+	select SOC_FAMILY_STM32
+	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
+	select HAS_STM32CUBE
+	select CPU_HAS_SYSTICK
+	help
+	  Enable support for stm32f2 MCU series

arch/arm/soc/st_stm32/stm32f2/dts.fixup

@@ -0,0 +1,3 @@
+/* SoC level DTS fixup file */
+
+/* End of SoC Level DTS fixup file */

arch/arm/soc/st_stm32/stm32f2/linker.ld

@@ -0,0 +1,9 @@
+/* linker.ld - Linker command/script file */
+
+/*
+ * Copyright (c) 2018 qianfan Zhao <qianfanguijin@163.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arch/arm/cortex_m/scripts/linker.ld>

arch/arm/soc/st_stm32/stm32f2/soc.c

@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2018 qianfan Zhao <qianfanguijin@163.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for stm32f2 processor
+ */
+
+#include <kernel.h>
+#include <device.h>
+#include <init.h>
+#include <soc.h>
+#include <arch/cpu.h>
+#include <cortex_m/exc.h>
+#include <linker/linker-defs.h>
+#include <string.h>
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ * So the init priority has to be 0 (zero).
+ *
+ * @return 0
+ */
+static int stm32f2_init(struct device *arg)
+{
+	u32_t key;
+
+	ARG_UNUSED(arg);
+
+	key = irq_lock();
+
+	_ClearFaults();
+
+	/* Install default handler that simply resets the CPU
+	 * if configured in the kernel, NOP otherwise
+	 */
+	NMI_INIT();
+
+	irq_unlock(key);
+
+	/* Update CMSIS SystemCoreClock variable (HCLK) */
+	/* At reset, system core clock is set to 16 MHz from HSI */
+	SystemCoreClock = 16000000;
+
+	return 0;
+}
+
+SYS_INIT(stm32f2_init, PRE_KERNEL_1, 0);

arch/arm/soc/st_stm32/stm32f2/soc.h

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2018 qianfan Zhao <qianfanguijin@163.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the stm32f2 family processors.
+ *
+ * Based on reference manual:
+ *   stm32f2X advanced ARM ® -based 32-bit MCUs
+ *
+ * Chapter 2.2: Memory organization
+ */
+
+
+#ifndef _STM32F2_SOC_H_
+#define _STM32F2_SOC_H_
+
+#define GPIO_REG_SIZE         0x400
+/* base address for where GPIO registers start */
+#define GPIO_PORTS_BASE       (GPIOA_BASE)
+
+#ifndef _ASMLANGUAGE
+
+#include <device.h>
+#include <misc/util.h>
+#include <random/rand32.h>
+
+#include <stm32f2xx.h>
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _STM32F2_SOC_H_ */

dts/arm/st/stm32f2-pinctrl.dtsi

@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2018 qianfan Zhao
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/stm32-pinctrl.h>
+
+/ {
+	soc {
+	};
+};

dts/arm/st/stm32f2.dtsi

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2018 qianfan Zhao
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <st/mem.h>
+#include <st/stm32f2-pinctrl.dtsi>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m3";
+			reg = <0>;
+		};
+	};
+
+	sram0: memory@20000000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x20000000 DT_SRAM_SIZE>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@8000000 {
+				compatible = "soc-nv-flash";
+				label = "FLASH_STM32";
+				reg = <0x08000000 DT_FLASH_SIZE>;
+
+				write-block-size = <1>;
+			};
+		};
+	};
+};