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dts: add SPI bindings for nRF family

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This change adds DTS definition of SPI device for nRF chips.
It also removes SPI pin configuration from Kconfig and moves it to
chip DTS.

Signed-off-by: Filip Kubicz <filip.kubicz@nordicsemi.no>
This commit is contained in:
Filip Kubicz 2018-09-04 15:03:58 +02:00 • committed by Carles Cufí
commit 990a0e8c71
20 changed files with 322 additions and 138 deletions
Download patch file Download diff file Expand all files Collapse all files

18
arch/arm/soc/nordic_nrf/nrf51/dts.fixup
View file

@ -34,6 +34,24 @@
#define CONFIG_I2C_1_SDA_PIN NORDIC_NRF_I2C_40004000_SDA_PIN
#define CONFIG_I2C_1_SCL_PIN NORDIC_NRF_I2C_40004000_SCL_PIN
#define CONFIG_SPI_0_BASE_ADDRESS NORDIC_NRF_SPI_40003000_BASE_ADDRESS
#define CONFIG_SPI_0_NAME NORDIC_NRF_SPI_40003000_LABEL
#define CONFIG_SPI_0_IRQ_PRI NORDIC_NRF_SPI_40003000_IRQ_0_PRIORITY
#define CONFIG_SPI_0_IRQ NORDIC_NRF_SPI_40003000_IRQ_0
#define CONFIG_SPI_0_NRF_SCK_PIN NORDIC_NRF_SPI_40003000_SCK_PIN
#define CONFIG_SPI_0_NRF_MOSI_PIN NORDIC_NRF_SPI_40003000_MOSI_PIN
#define CONFIG_SPI_0_NRF_MISO_PIN NORDIC_NRF_SPI_40003000_MISO_PIN
#define CONFIG_SPI_0_NRF_CSN_PIN NORDIC_NRF_SPI_40003000_CSN_PIN
#define CONFIG_SPI_1_BASE_ADDRESS NORDIC_NRF_SPI_40004000_BASE_ADDRESS
#define CONFIG_SPI_1_NAME NORDIC_NRF_SPI_40004000_LABEL
#define CONFIG_SPI_1_IRQ_PRI NORDIC_NRF_SPI_40004000_IRQ_0_PRIORITY
#define CONFIG_SPI_1_IRQ NORDIC_NRF_SPI_40004000_IRQ_0
#define CONFIG_SPI_1_NRF_SCK_PIN NORDIC_NRF_SPI_40004000_SCK_PIN
#define CONFIG_SPI_1_NRF_MOSI_PIN NORDIC_NRF_SPI_40004000_MOSI_PIN
#define CONFIG_SPI_1_NRF_MISO_PIN NORDIC_NRF_SPI_40004000_MISO_PIN
#define CONFIG_SPI_1_NRF_CSN_PIN NORDIC_NRF_SPI_40004000_CSN_PIN
#define CONFIG_WDT_0_NAME NORDIC_NRF_WATCHDOG_40010000_LABEL
#define CONFIG_WDT_NRF_IRQ NORDIC_NRF_WATCHDOG_40010000_IRQ_WDT
#define CONFIG_WDT_NRF_IRQ_PRI NORDIC_NRF_WATCHDOG_40010000_IRQ_WDT_PRIORITY

36
arch/arm/soc/nordic_nrf/nrf52/dts.fixup
View file

@ -51,6 +51,42 @@
#define CONFIG_I2C_1_SDA_PIN NORDIC_NRF_I2C_40004000_SDA_PIN
#define CONFIG_I2C_1_SCL_PIN NORDIC_NRF_I2C_40004000_SCL_PIN
#define CONFIG_SPI_0_BASE_ADDRESS NORDIC_NRF_SPI_40003000_BASE_ADDRESS
#define CONFIG_SPI_0_NAME NORDIC_NRF_SPI_40003000_LABEL
#define CONFIG_SPI_0_IRQ_PRI NORDIC_NRF_SPI_40003000_IRQ_0_PRIORITY
#define CONFIG_SPI_0_IRQ NORDIC_NRF_SPI_40003000_IRQ_0
#define CONFIG_SPI_0_NRF_SCK_PIN NORDIC_NRF_SPI_40003000_SCK_PIN
#define CONFIG_SPI_0_NRF_MOSI_PIN NORDIC_NRF_SPI_40003000_MOSI_PIN
#define CONFIG_SPI_0_NRF_MISO_PIN NORDIC_NRF_SPI_40003000_MISO_PIN
#define CONFIG_SPI_0_NRF_CSN_PIN NORDIC_NRF_SPI_40003000_CSN_PIN
#define CONFIG_SPI_1_BASE_ADDRESS NORDIC_NRF_SPI_40004000_BASE_ADDRESS
#define CONFIG_SPI_1_NAME NORDIC_NRF_SPI_40004000_LABEL
#define CONFIG_SPI_1_IRQ_PRI NORDIC_NRF_SPI_40004000_IRQ_0_PRIORITY
#define CONFIG_SPI_1_IRQ NORDIC_NRF_SPI_40004000_IRQ_0
#define CONFIG_SPI_1_NRF_SCK_PIN NORDIC_NRF_SPI_40004000_SCK_PIN
#define CONFIG_SPI_1_NRF_MOSI_PIN NORDIC_NRF_SPI_40004000_MOSI_PIN
#define CONFIG_SPI_1_NRF_MISO_PIN NORDIC_NRF_SPI_40004000_MISO_PIN
#define CONFIG_SPI_1_NRF_CSN_PIN NORDIC_NRF_SPI_40004000_CSN_PIN
#define CONFIG_SPI_2_BASE_ADDRESS NORDIC_NRF_SPI_40023000_BASE_ADDRESS
#define CONFIG_SPI_2_NAME NORDIC_NRF_SPI_40023000_LABEL
#define CONFIG_SPI_2_IRQ_PRI NORDIC_NRF_SPI_40023000_IRQ_0_PRIORITY
#define CONFIG_SPI_2_IRQ NORDIC_NRF_SPI_40023000_IRQ_0
#define CONFIG_SPI_2_NRF_SCK_PIN NORDIC_NRF_SPI_40023000_SCK_PIN
#define CONFIG_SPI_2_NRF_MOSI_PIN NORDIC_NRF_SPI_40023000_MOSI_PIN
#define CONFIG_SPI_2_NRF_MISO_PIN NORDIC_NRF_SPI_40023000_MISO_PIN
#define CONFIG_SPI_2_NRF_CSN_PIN NORDIC_NRF_SPI_40023000_CSN_PIN
#define CONFIG_SPI_3_BASE_ADDRESS NORDIC_NRF_SPI_4002B000_BASE_ADDRESS
#define CONFIG_SPI_3_NAME NORDIC_NRF_SPI_4002B000_LABEL
#define CONFIG_SPI_3_IRQ_PRI NORDIC_NRF_SPI_4002B000_IRQ_0_PRIORITY
#define CONFIG_SPI_3_IRQ NORDIC_NRF_SPI_4002B000_IRQ_0
#define CONFIG_SPI_3_NRF_SCK_PIN NORDIC_NRF_SPI_4002B000_SCK_PIN
#define CONFIG_SPI_3_NRF_MOSI_PIN NORDIC_NRF_SPI_4002B000_MOSI_PIN
#define CONFIG_SPI_3_NRF_MISO_PIN NORDIC_NRF_SPI_4002B000_MISO_PIN
#define CONFIG_SPI_3_NRF_CSN_PIN NORDIC_NRF_SPI_4002B000_CSN_PIN
#define CONFIG_USBD_NRF5_IRQ NORDIC_NRF_USBD_40027000_IRQ_USBD
#define CONFIG_USBD_NRF5_IRQ_PRI NORDIC_NRF_USBD_40027000_IRQ_USBD_PRIORITY
#define CONFIG_USBD_NRF5_NUM_BIDIR_EP NORDIC_NRF_USBD_40027000_NUM_BIDIR_ENDPOINTS

8
boards/arm/96b_carbon_nrf51/96b_carbon_nrf51.dts
View file

@ -31,3 +31,11 @@
current-speed = <115200>;
status = "ok";
};
&spi1 {
status = "ok";
sck-pin = <7>;
mosi-pin = <0>;
miso-pin = <30>;
csn-pin = <25>;
};

7
boards/arm/96b_carbon_nrf51/96b_carbon_nrf51_defconfig
View file

@ -25,11 +25,6 @@ CONFIG_BT_CTLR_TO_HOST_SPI_IRQ_PIN=28
# spi
CONFIG_SPI=y
CONFIG_SPI_1=y
CONFIG_SPI_1_NAME="SPI_1"
CONFIG_SPI_1_IRQ_PRI=1
CONFIG_SPI_NRFX=y
CONFIG_SPI_SLAVE=y
CONFIG_SPI_1_NRF_SPIS=y
CONFIG_SPI_1_NRF_SCK_PIN=7
CONFIG_SPI_1_NRF_MOSI_PIN=0
CONFIG_SPI_1_NRF_MISO_PIN=30
CONFIG_SPI_1_NRF_CSN_PIN=25

14
boards/arm/nrf51_pca10028/nrf51_pca10028.dts
View file

@ -51,6 +51,20 @@
scl-pin = <6>;
};
&spi0 {
status = "ok";
sck-pin = <7>;
mosi-pin = <29>;
miso-pin = <30>;
};
&spi1 {
status = "ok";
sck-pin = <6>;
mosi-pin = <5>;
miso-pin = <4>;
};
&flash0 {
/*
* For more information, see:

7
boards/arm/nrf52810_pca10040/nrf52810_pca10040.dts
View file

@ -89,6 +89,13 @@
scl-pin = <27>;
};
&spi0 {
status = "ok";
sck-pin = <29>;
mosi-pin = <31>;
miso-pin = <30>;
};
&flash0 {
/*
* For more information, see:

28
boards/arm/nrf52840_pca10056/nrf52840_pca10056.dts
View file

@ -76,6 +76,34 @@
scl-pin = <31>;
};
&spi0 {
status = "ok";
sck-pin = <27>;
mosi-pin = <26>;
miso-pin = <29>;
};
&spi1 {
status = "ok";
sck-pin = <31>;
mosi-pin = <30>;
miso-pin = <40>;
};
&spi2 {
status = "ok";
sck-pin = <43>;
mosi-pin = <44>;
miso-pin = <45>;
};
&spi3 {
status = "ok";
sck-pin = <42>;
mosi-pin = <41>;
miso-pin = <20>;
};
&flash0 {
/*
* For more information, see:

18
boards/arm/nrf52840_pca10059/nrf52840_pca10059.dts
View file

@ -87,6 +87,24 @@
scl-pin = <31>;
};
/*
* By default, not adding all available SPI instances (spi2, spi3) due to
* limited GPIOs available on dongle board.
*/
&spi0 {
status = "ok";
sck-pin = <27>;
mosi-pin = <26>;
miso-pin = <42>;
};
&spi1 {
status = "ok";
sck-pin = <31>;
mosi-pin = <30>;
miso-pin = <45>;
};
&flash0 {
/*
* For more information, see:

21
boards/arm/nrf52_pca10040/nrf52_pca10040.dts
View file

@ -53,6 +53,27 @@
scl-pin = <31>;
};
&spi0 {
status = "ok";
sck-pin = <27>;
mosi-pin = <26>;
miso-pin = <25>;
};
&spi1 {
status = "ok";
sck-pin = <31>;
mosi-pin = <30>;
miso-pin = <29>;
};
&spi2 {
status = "ok";
sck-pin = <22>;
mosi-pin = <23>;
miso-pin = <24>;
};
&flash0 {
/*
* For more information, see:

12
boards/arm/reel_board/Kconfig.defconfig
View file

@ -83,18 +83,6 @@ if SPI_3
config SPI_3_NRF_SPIM
def_bool y
config SPI_3_IRQ_PRI
default 1
config SPI_3_NRF_SCK_PIN
default 19
config SPI_3_NRF_MOSI_PIN
default 20
config SPI_3_NRF_MISO_PIN
default 21
config SPI_3_NRF_RX_DELAY
default 1

7
boards/arm/reel_board/reel_board.dts
View file

@ -105,6 +105,13 @@
};
};
&spi3 {
status = "ok";
sck-pin = <19>;
mosi-pin = <20>;
miso-pin = <21>;
};
&flash0 {
/*
* For more information, see:

106
drivers/spi/Kconfig.nrfx
View file

@ -6,6 +6,7 @@
menuconfig SPI_NRFX
bool "nRF SPI nrfx drivers"
depends on SOC_FAMILY_NRF
select HAS_DTS_SPI
help
Enable support for nrfx SPI drivers for nRF MCU series.
Peripherals with the same instance ID cannot be used together,
@ -52,27 +53,6 @@ endchoice
if SPI_0_NRF_SPI || SPI_0_NRF_SPIM || SPI_0_NRF_SPIS
config SPI_0_NRF_SCK_PIN
int "SCK pin number"
range 0 47 if SOC_NRF52840_QIAA
range 0 31
help
GPIO pin number to use for SCK.
config SPI_0_NRF_MOSI_PIN
int "MOSI pin number"
range 0 47 if SOC_NRF52840_QIAA
range 0 31
help
GPIO pin number to use for MOSI.
config SPI_0_NRF_MISO_PIN
int "MISO pin number"
range 0 47 if SOC_NRF52840_QIAA
range 0 31
help
GPIO pin number to use for MISO.
config SPI_0_NRF_ORC
hex "Over-read Character"
range 0x00 0xff
@ -85,13 +65,6 @@ endif # SPI_0_NRF_SPI || SPI_0_NRF_SPIM || SPI_0_NRF_SPIS
if SPI_0_NRF_SPIS
config SPI_0_NRF_CSN_PIN
int "CSN pin number"
range 0 47 if SOC_NRF52840_QIAA
range 0 31
help
GPIO pin number to use for Chip Select.
config SPI_0_NRF_DEF
hex "Default Character"
range 0x00 0xff
@ -140,27 +113,6 @@ endchoice
if SPI_1_NRF_SPI || SPI_1_NRF_SPIM || SPI_1_NRF_SPIS
config SPI_1_NRF_SCK_PIN
int "SCK pin number"
range 0 47 if SOC_NRF52840_QIAA
range 0 31
help
GPIO pin number to use for SCK.
config SPI_1_NRF_MOSI_PIN
int "MOSI pin number"
range 0 47 if SOC_NRF52840_QIAA
range 0 31
help
GPIO pin number to use for MOSI.
config SPI_1_NRF_MISO_PIN
int "MISO pin number"
range 0 47 if SOC_NRF52840_QIAA
range 0 31
help
GPIO pin number to use for MISO.
config SPI_1_NRF_ORC
hex "Over-read Character"
range 0x00 0xff
@ -173,13 +125,6 @@ endif # SPI_1_NRF_SPI || SPI_1_NRF_SPIM || SPI_1_NRF_SPIS
if SPI_1_NRF_SPIS
config SPI_1_NRF_CSN_PIN
int "CSN pin number"
range 0 47 if SOC_NRF52840_QIAA
range 0 31
help
GPIO pin number to use for Chip Select.
config SPI_1_NRF_DEF
hex "Default Character"
range 0x00 0xff
@ -227,27 +172,6 @@ endchoice
if SPI_2_NRF_SPI || SPI_2_NRF_SPIM || SPI_2_NRF_SPIS
config SPI_2_NRF_SCK_PIN
int "SCK pin number"
range 0 47 if SOC_NRF52840_QIAA
range 0 31
help
GPIO pin number to use for SCK.
config SPI_2_NRF_MOSI_PIN
int "MOSI pin number"
range 0 47 if SOC_NRF52840_QIAA
range 0 31
help
GPIO pin number to use for MOSI.
config SPI_2_NRF_MISO_PIN
int "MISO pin number"
range 0 47 if SOC_NRF52840_QIAA
range 0 31
help
GPIO pin number to use for MISO.
config SPI_2_NRF_ORC
hex "Over-read Character"
range 0x00 0xff
@ -260,13 +184,6 @@ endif # SPI_2_NRF_SPI || SPI_2_NRF_SPIM || SPI_2_NRF_SPIS
if SPI_2_NRF_SPIS
config SPI_2_NRF_CSN_PIN
int "CSN pin number"
range 0 47 if SOC_NRF52840_QIAA
range 0 31
help
GPIO pin number to use for Chip Select.
config SPI_2_NRF_DEF
hex "Default Character"
range 0x00 0xff
@ -289,27 +206,6 @@ config SPI_3_NRF_SPIM
if SPI_3_NRF_SPIM
config SPI_3_NRF_SCK_PIN
int "SCK pin number"
range 0 47 if SOC_NRF52840_QIAA
range 0 31
help
GPIO pin number to use for SCK
config SPI_3_NRF_MOSI_PIN
int "MOSI pin number"
range 0 47 if SOC_NRF52840_QIAA
range 0 31
help
GPIO pin number to use for MOSI
config SPI_3_NRF_MISO_PIN
int "MISO pin number"
range 0 47 if SOC_NRF52840_QIAA
range 0 31
help
GPIO pin number to use for MISO
config SPI_3_NRF_ORC
hex "Over-read Character"
range 0x00 0xff

20
dts/arm/nordic/nrf51822.dtsi
View file

@ -95,6 +95,26 @@
label = "I2C_1";
};
spi0: spi@40003000 {
compatible = "nordic,nrf-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003000 0x1000>;
interrupts = <3 1>;
status = "disabled";
label = "SPI_0";
};
spi1: spi@40004000 {
compatible = "nordic,nrf-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40004000 0x1000>;
interrupts = <4 1>;
status = "disabled";
label = "SPI_1";
};
wdt: watchdog@40010000 {
compatible = "nordic,nrf-watchdog";
reg = <0x40010000 0x1000>;

10
dts/arm/nordic/nrf52810.dtsi
View file

@ -85,6 +85,16 @@
label = "I2C_0";
};
spi0: spi@40004000 {
compatible = "nordic,nrf-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40004000 0x1000>;
interrupts = <4 1>;
status = "disabled";
label = "SPI_0";
};
wdt: watchdog@40010000 {
compatible = "nordic,nrf-watchdog";
reg = <0x40010000 0x1000>;

30
dts/arm/nordic/nrf52832.dtsi
View file

@ -97,6 +97,36 @@
label = "I2C_1";
};
spi0: spi@40003000 {
compatible = "nordic,nrf-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003000 0x1000>;
interrupts = <3 1>;
status = "disabled";
label = "SPI_0";
};
spi1: spi@40004000 {
compatible = "nordic,nrf-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40004000 0x1000>;
interrupts = <4 1>;
status = "disabled";
label = "SPI_1";
};
spi2: spi@40023000 {
compatible = "nordic,nrf-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40023000 0x1000>;
interrupts = <35 1>;
status = "disabled";
label = "SPI_2";
};
wdt: watchdog@40010000 {
compatible = "nordic,nrf-watchdog";
reg = <0x40010000 0x1000>;

40
dts/arm/nordic/nrf52840.dtsi
View file

@ -116,6 +116,46 @@
label = "I2C_1";
};
spi0: spi@40003000 {
compatible = "nordic,nrf-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003000 0x1000>;
interrupts = <3 1>;
status = "disabled";
label = "SPI_0";
};
spi1: spi@40004000 {
compatible = "nordic,nrf-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40004000 0x1000>;
interrupts = <4 1>;
status = "disabled";
label = "SPI_1";
};
spi2: spi@40023000 {
compatible = "nordic,nrf-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40023000 0x1000>;
interrupts = <35 1>;
status = "disabled";
label = "SPI_2";
};
spi3: spi@4002B000 {
compatible = "nordic,nrf-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4002B000 0x1000>;
interrupts = <47 1>;
status = "disabled";
label = "SPI_3";
};
usbd: usbd@40027000 {
compatible = "nordic,nrf-usbd";
reg = <0x40027000 0x1000>;

60
dts/bindings/spi/nordic,nrf-spi.yaml Normal file
View file

@ -0,0 +1,60 @@
#
# Copyright (c) 2018 Nordic Semiconductor ASA
#
# SPDX-License-Identifier: BSD-5-Clause-Nordic
#
---
title: Nordic nRF Family SPI Master node
id: nordic,nrf-spi
version: 0.1
description: >
This is a representation of the Nordic nRF SPI node
inherits:
!include spi.yaml
properties:
compatible:
type: string
category: required
description: compatible strings
constraint: "nordic,nrf-spi"
reg:
type: array
description: mmio register space
generation: define
category: required
interrupts:
type: array
category: required
description: required interrupts
generation: define
sck-pin:
type: int
description: SCK pin
generation: define
category: required
mosi-pin:
type: int
description: MOSI pin
generation: define
category: required
miso-pin:
type: int
description: MISO pin
generation: define
category: required
csn-pin:
type: int
description: CSN pin
generation: define
category: optional
...

6
tests/drivers/spi/spi_loopback/boards/nrf51_pca10028.conf
View file

@ -1,12 +1,8 @@
CONFIG_SPI_NRFX=y
CONFIG_SPI_0=y
CONFIG_SPI_0_IRQ_PRI=1
CONFIG_SPI_0_NRF_SPI=y
CONFIG_SPI_0_NRF_SCK_PIN=4
CONFIG_SPI_0_NRF_MOSI_PIN=6
CONFIG_SPI_0_NRF_MISO_PIN=5
CONFIG_SPI_LOOPBACK_DRV_NAME="SPI_0"
CONFIG_SPI_LOOPBACK_CS_GPIO=y
CONFIG_SPI_LOOPBACK_CS_CTRL_GPIO_DRV_NAME="GPIO_0"
CONFIG_SPI_LOOPBACK_CS_CTRL_GPIO_PIN=30
CONFIG_SPI_LOOPBACK_CS_CTRL_GPIO_PIN=28

6
tests/drivers/spi/spi_loopback/boards/nrf52840_pca10056.conf
View file

@ -1,14 +1,10 @@
CONFIG_SPI_NRFX=y
CONFIG_SPI_NRFX_RAM_BUFFER_SIZE=8
CONFIG_SPI_3=y
CONFIG_SPI_3_IRQ_PRI=1
CONFIG_SPI_3_NRF_SPIM=y
CONFIG_SPI_3_NRF_SCK_PIN=29
CONFIG_SPI_3_NRF_MOSI_PIN=31
CONFIG_SPI_3_NRF_MISO_PIN=30
CONFIG_SPI_3_NRF_RX_DELAY=1
CONFIG_SPI_LOOPBACK_DRV_NAME="SPI_3"
CONFIG_SPI_LOOPBACK_CS_GPIO=y
CONFIG_SPI_LOOPBACK_CS_CTRL_GPIO_DRV_NAME="GPIO_0"
CONFIG_SPI_LOOPBACK_CS_CTRL_GPIO_PIN=26
CONFIG_SPI_LOOPBACK_CS_CTRL_GPIO_PIN=28

6
tests/drivers/spi/spi_loopback/boards/nrf52_pca10040.conf
View file

@ -1,12 +1,8 @@
CONFIG_SPI_NRFX=y
CONFIG_SPI_1=y
CONFIG_SPI_1_IRQ_PRI=1
CONFIG_SPI_1_NRF_SPI=y
CONFIG_SPI_1_NRF_SCK_PIN=29
CONFIG_SPI_1_NRF_MOSI_PIN=31
CONFIG_SPI_1_NRF_MISO_PIN=30
CONFIG_SPI_LOOPBACK_DRV_NAME="SPI_1"
CONFIG_SPI_LOOPBACK_CS_GPIO=y
CONFIG_SPI_LOOPBACK_CS_CTRL_GPIO_DRV_NAME="GPIO_0"
CONFIG_SPI_LOOPBACK_CS_CTRL_GPIO_PIN=26
CONFIG_SPI_LOOPBACK_CS_CTRL_GPIO_PIN=28