dts: add SPI bindings for nRF family
This change adds DTS definition of SPI device for nRF chips. It also removes SPI pin configuration from Kconfig and moves it to chip DTS. Signed-off-by: Filip Kubicz <filip.kubicz@nordicsemi.no>
This commit is contained in:
parent
5c3992f34f
commit
990a0e8c71
20 changed files with 322 additions and 138 deletions
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@ -34,6 +34,24 @@
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#define CONFIG_I2C_1_SDA_PIN NORDIC_NRF_I2C_40004000_SDA_PIN
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#define CONFIG_I2C_1_SCL_PIN NORDIC_NRF_I2C_40004000_SCL_PIN
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#define CONFIG_SPI_0_BASE_ADDRESS NORDIC_NRF_SPI_40003000_BASE_ADDRESS
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#define CONFIG_SPI_0_NAME NORDIC_NRF_SPI_40003000_LABEL
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#define CONFIG_SPI_0_IRQ_PRI NORDIC_NRF_SPI_40003000_IRQ_0_PRIORITY
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#define CONFIG_SPI_0_IRQ NORDIC_NRF_SPI_40003000_IRQ_0
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#define CONFIG_SPI_0_NRF_SCK_PIN NORDIC_NRF_SPI_40003000_SCK_PIN
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#define CONFIG_SPI_0_NRF_MOSI_PIN NORDIC_NRF_SPI_40003000_MOSI_PIN
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#define CONFIG_SPI_0_NRF_MISO_PIN NORDIC_NRF_SPI_40003000_MISO_PIN
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#define CONFIG_SPI_0_NRF_CSN_PIN NORDIC_NRF_SPI_40003000_CSN_PIN
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#define CONFIG_SPI_1_BASE_ADDRESS NORDIC_NRF_SPI_40004000_BASE_ADDRESS
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#define CONFIG_SPI_1_NAME NORDIC_NRF_SPI_40004000_LABEL
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#define CONFIG_SPI_1_IRQ_PRI NORDIC_NRF_SPI_40004000_IRQ_0_PRIORITY
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#define CONFIG_SPI_1_IRQ NORDIC_NRF_SPI_40004000_IRQ_0
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#define CONFIG_SPI_1_NRF_SCK_PIN NORDIC_NRF_SPI_40004000_SCK_PIN
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#define CONFIG_SPI_1_NRF_MOSI_PIN NORDIC_NRF_SPI_40004000_MOSI_PIN
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#define CONFIG_SPI_1_NRF_MISO_PIN NORDIC_NRF_SPI_40004000_MISO_PIN
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#define CONFIG_SPI_1_NRF_CSN_PIN NORDIC_NRF_SPI_40004000_CSN_PIN
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#define CONFIG_WDT_0_NAME NORDIC_NRF_WATCHDOG_40010000_LABEL
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#define CONFIG_WDT_NRF_IRQ NORDIC_NRF_WATCHDOG_40010000_IRQ_WDT
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#define CONFIG_WDT_NRF_IRQ_PRI NORDIC_NRF_WATCHDOG_40010000_IRQ_WDT_PRIORITY
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@ -51,6 +51,42 @@
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#define CONFIG_I2C_1_SDA_PIN NORDIC_NRF_I2C_40004000_SDA_PIN
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#define CONFIG_I2C_1_SCL_PIN NORDIC_NRF_I2C_40004000_SCL_PIN
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#define CONFIG_SPI_0_BASE_ADDRESS NORDIC_NRF_SPI_40003000_BASE_ADDRESS
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#define CONFIG_SPI_0_NAME NORDIC_NRF_SPI_40003000_LABEL
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#define CONFIG_SPI_0_IRQ_PRI NORDIC_NRF_SPI_40003000_IRQ_0_PRIORITY
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#define CONFIG_SPI_0_IRQ NORDIC_NRF_SPI_40003000_IRQ_0
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#define CONFIG_SPI_0_NRF_SCK_PIN NORDIC_NRF_SPI_40003000_SCK_PIN
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#define CONFIG_SPI_0_NRF_MOSI_PIN NORDIC_NRF_SPI_40003000_MOSI_PIN
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#define CONFIG_SPI_0_NRF_MISO_PIN NORDIC_NRF_SPI_40003000_MISO_PIN
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#define CONFIG_SPI_0_NRF_CSN_PIN NORDIC_NRF_SPI_40003000_CSN_PIN
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#define CONFIG_SPI_1_BASE_ADDRESS NORDIC_NRF_SPI_40004000_BASE_ADDRESS
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#define CONFIG_SPI_1_NAME NORDIC_NRF_SPI_40004000_LABEL
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#define CONFIG_SPI_1_IRQ_PRI NORDIC_NRF_SPI_40004000_IRQ_0_PRIORITY
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#define CONFIG_SPI_1_IRQ NORDIC_NRF_SPI_40004000_IRQ_0
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#define CONFIG_SPI_1_NRF_SCK_PIN NORDIC_NRF_SPI_40004000_SCK_PIN
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#define CONFIG_SPI_1_NRF_MOSI_PIN NORDIC_NRF_SPI_40004000_MOSI_PIN
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#define CONFIG_SPI_1_NRF_MISO_PIN NORDIC_NRF_SPI_40004000_MISO_PIN
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#define CONFIG_SPI_1_NRF_CSN_PIN NORDIC_NRF_SPI_40004000_CSN_PIN
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#define CONFIG_SPI_2_BASE_ADDRESS NORDIC_NRF_SPI_40023000_BASE_ADDRESS
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#define CONFIG_SPI_2_NAME NORDIC_NRF_SPI_40023000_LABEL
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#define CONFIG_SPI_2_IRQ_PRI NORDIC_NRF_SPI_40023000_IRQ_0_PRIORITY
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#define CONFIG_SPI_2_IRQ NORDIC_NRF_SPI_40023000_IRQ_0
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#define CONFIG_SPI_2_NRF_SCK_PIN NORDIC_NRF_SPI_40023000_SCK_PIN
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#define CONFIG_SPI_2_NRF_MOSI_PIN NORDIC_NRF_SPI_40023000_MOSI_PIN
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#define CONFIG_SPI_2_NRF_MISO_PIN NORDIC_NRF_SPI_40023000_MISO_PIN
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#define CONFIG_SPI_2_NRF_CSN_PIN NORDIC_NRF_SPI_40023000_CSN_PIN
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#define CONFIG_SPI_3_BASE_ADDRESS NORDIC_NRF_SPI_4002B000_BASE_ADDRESS
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#define CONFIG_SPI_3_NAME NORDIC_NRF_SPI_4002B000_LABEL
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#define CONFIG_SPI_3_IRQ_PRI NORDIC_NRF_SPI_4002B000_IRQ_0_PRIORITY
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#define CONFIG_SPI_3_IRQ NORDIC_NRF_SPI_4002B000_IRQ_0
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#define CONFIG_SPI_3_NRF_SCK_PIN NORDIC_NRF_SPI_4002B000_SCK_PIN
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#define CONFIG_SPI_3_NRF_MOSI_PIN NORDIC_NRF_SPI_4002B000_MOSI_PIN
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#define CONFIG_SPI_3_NRF_MISO_PIN NORDIC_NRF_SPI_4002B000_MISO_PIN
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#define CONFIG_SPI_3_NRF_CSN_PIN NORDIC_NRF_SPI_4002B000_CSN_PIN
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#define CONFIG_USBD_NRF5_IRQ NORDIC_NRF_USBD_40027000_IRQ_USBD
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#define CONFIG_USBD_NRF5_IRQ_PRI NORDIC_NRF_USBD_40027000_IRQ_USBD_PRIORITY
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#define CONFIG_USBD_NRF5_NUM_BIDIR_EP NORDIC_NRF_USBD_40027000_NUM_BIDIR_ENDPOINTS
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@ -31,3 +31,11 @@
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current-speed = <115200>;
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status = "ok";
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};
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&spi1 {
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status = "ok";
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sck-pin = <7>;
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mosi-pin = <0>;
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miso-pin = <30>;
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csn-pin = <25>;
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};
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@ -25,11 +25,6 @@ CONFIG_BT_CTLR_TO_HOST_SPI_IRQ_PIN=28
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# spi
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CONFIG_SPI=y
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CONFIG_SPI_1=y
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CONFIG_SPI_1_NAME="SPI_1"
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CONFIG_SPI_1_IRQ_PRI=1
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CONFIG_SPI_NRFX=y
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CONFIG_SPI_SLAVE=y
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CONFIG_SPI_1_NRF_SPIS=y
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CONFIG_SPI_1_NRF_SCK_PIN=7
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CONFIG_SPI_1_NRF_MOSI_PIN=0
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CONFIG_SPI_1_NRF_MISO_PIN=30
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CONFIG_SPI_1_NRF_CSN_PIN=25
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@ -51,6 +51,20 @@
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scl-pin = <6>;
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};
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&spi0 {
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status = "ok";
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sck-pin = <7>;
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mosi-pin = <29>;
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miso-pin = <30>;
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};
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&spi1 {
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status = "ok";
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sck-pin = <6>;
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mosi-pin = <5>;
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miso-pin = <4>;
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};
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&flash0 {
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/*
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* For more information, see:
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@ -89,6 +89,13 @@
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scl-pin = <27>;
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};
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&spi0 {
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status = "ok";
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sck-pin = <29>;
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mosi-pin = <31>;
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miso-pin = <30>;
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};
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&flash0 {
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/*
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* For more information, see:
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@ -76,6 +76,34 @@
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scl-pin = <31>;
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};
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&spi0 {
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status = "ok";
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sck-pin = <27>;
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mosi-pin = <26>;
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miso-pin = <29>;
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};
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&spi1 {
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status = "ok";
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sck-pin = <31>;
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mosi-pin = <30>;
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miso-pin = <40>;
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};
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&spi2 {
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status = "ok";
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sck-pin = <43>;
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mosi-pin = <44>;
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miso-pin = <45>;
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};
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&spi3 {
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status = "ok";
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sck-pin = <42>;
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mosi-pin = <41>;
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miso-pin = <20>;
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};
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&flash0 {
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/*
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* For more information, see:
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@ -87,6 +87,24 @@
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scl-pin = <31>;
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};
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/*
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* By default, not adding all available SPI instances (spi2, spi3) due to
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* limited GPIOs available on dongle board.
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*/
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&spi0 {
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status = "ok";
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sck-pin = <27>;
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mosi-pin = <26>;
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miso-pin = <42>;
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};
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&spi1 {
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status = "ok";
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sck-pin = <31>;
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mosi-pin = <30>;
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miso-pin = <45>;
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};
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&flash0 {
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/*
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* For more information, see:
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@ -53,6 +53,27 @@
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scl-pin = <31>;
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};
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&spi0 {
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status = "ok";
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sck-pin = <27>;
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mosi-pin = <26>;
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miso-pin = <25>;
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};
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&spi1 {
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status = "ok";
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sck-pin = <31>;
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mosi-pin = <30>;
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miso-pin = <29>;
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};
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&spi2 {
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status = "ok";
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sck-pin = <22>;
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mosi-pin = <23>;
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miso-pin = <24>;
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};
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&flash0 {
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/*
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* For more information, see:
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@ -83,18 +83,6 @@ if SPI_3
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config SPI_3_NRF_SPIM
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def_bool y
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config SPI_3_IRQ_PRI
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default 1
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config SPI_3_NRF_SCK_PIN
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default 19
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config SPI_3_NRF_MOSI_PIN
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default 20
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config SPI_3_NRF_MISO_PIN
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default 21
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config SPI_3_NRF_RX_DELAY
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default 1
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@ -105,6 +105,13 @@
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};
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};
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&spi3 {
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status = "ok";
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sck-pin = <19>;
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mosi-pin = <20>;
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miso-pin = <21>;
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};
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&flash0 {
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/*
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* For more information, see:
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@ -6,6 +6,7 @@
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menuconfig SPI_NRFX
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bool "nRF SPI nrfx drivers"
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depends on SOC_FAMILY_NRF
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select HAS_DTS_SPI
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help
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Enable support for nrfx SPI drivers for nRF MCU series.
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Peripherals with the same instance ID cannot be used together,
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@ -52,27 +53,6 @@ endchoice
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if SPI_0_NRF_SPI || SPI_0_NRF_SPIM || SPI_0_NRF_SPIS
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config SPI_0_NRF_SCK_PIN
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int "SCK pin number"
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range 0 47 if SOC_NRF52840_QIAA
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range 0 31
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help
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GPIO pin number to use for SCK.
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config SPI_0_NRF_MOSI_PIN
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int "MOSI pin number"
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range 0 47 if SOC_NRF52840_QIAA
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range 0 31
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help
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GPIO pin number to use for MOSI.
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config SPI_0_NRF_MISO_PIN
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int "MISO pin number"
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range 0 47 if SOC_NRF52840_QIAA
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range 0 31
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help
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GPIO pin number to use for MISO.
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config SPI_0_NRF_ORC
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hex "Over-read Character"
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range 0x00 0xff
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@ -85,13 +65,6 @@ endif # SPI_0_NRF_SPI || SPI_0_NRF_SPIM || SPI_0_NRF_SPIS
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if SPI_0_NRF_SPIS
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config SPI_0_NRF_CSN_PIN
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int "CSN pin number"
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range 0 47 if SOC_NRF52840_QIAA
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range 0 31
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help
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GPIO pin number to use for Chip Select.
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config SPI_0_NRF_DEF
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hex "Default Character"
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range 0x00 0xff
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if SPI_1_NRF_SPI || SPI_1_NRF_SPIM || SPI_1_NRF_SPIS
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config SPI_1_NRF_SCK_PIN
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int "SCK pin number"
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range 0 47 if SOC_NRF52840_QIAA
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range 0 31
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help
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GPIO pin number to use for SCK.
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config SPI_1_NRF_MOSI_PIN
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int "MOSI pin number"
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range 0 47 if SOC_NRF52840_QIAA
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range 0 31
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help
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GPIO pin number to use for MOSI.
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config SPI_1_NRF_MISO_PIN
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int "MISO pin number"
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range 0 47 if SOC_NRF52840_QIAA
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range 0 31
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help
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GPIO pin number to use for MISO.
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config SPI_1_NRF_ORC
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hex "Over-read Character"
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range 0x00 0xff
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if SPI_1_NRF_SPIS
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config SPI_1_NRF_CSN_PIN
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int "CSN pin number"
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range 0 47 if SOC_NRF52840_QIAA
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range 0 31
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help
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GPIO pin number to use for Chip Select.
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config SPI_1_NRF_DEF
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hex "Default Character"
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range 0x00 0xff
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if SPI_2_NRF_SPI || SPI_2_NRF_SPIM || SPI_2_NRF_SPIS
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config SPI_2_NRF_SCK_PIN
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int "SCK pin number"
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range 0 47 if SOC_NRF52840_QIAA
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range 0 31
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help
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GPIO pin number to use for SCK.
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config SPI_2_NRF_MOSI_PIN
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int "MOSI pin number"
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range 0 47 if SOC_NRF52840_QIAA
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range 0 31
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help
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GPIO pin number to use for MOSI.
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config SPI_2_NRF_MISO_PIN
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int "MISO pin number"
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range 0 47 if SOC_NRF52840_QIAA
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range 0 31
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help
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GPIO pin number to use for MISO.
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config SPI_2_NRF_ORC
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hex "Over-read Character"
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range 0x00 0xff
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if SPI_2_NRF_SPIS
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config SPI_2_NRF_CSN_PIN
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int "CSN pin number"
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range 0 47 if SOC_NRF52840_QIAA
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range 0 31
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help
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GPIO pin number to use for Chip Select.
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config SPI_2_NRF_DEF
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hex "Default Character"
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range 0x00 0xff
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if SPI_3_NRF_SPIM
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config SPI_3_NRF_SCK_PIN
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int "SCK pin number"
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range 0 47 if SOC_NRF52840_QIAA
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range 0 31
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help
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GPIO pin number to use for SCK
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config SPI_3_NRF_MOSI_PIN
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int "MOSI pin number"
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range 0 47 if SOC_NRF52840_QIAA
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range 0 31
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help
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GPIO pin number to use for MOSI
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config SPI_3_NRF_MISO_PIN
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int "MISO pin number"
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range 0 47 if SOC_NRF52840_QIAA
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range 0 31
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help
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GPIO pin number to use for MISO
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config SPI_3_NRF_ORC
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hex "Over-read Character"
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range 0x00 0xff
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label = "I2C_1";
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};
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spi0: spi@40003000 {
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compatible = "nordic,nrf-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003000 0x1000>;
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interrupts = <3 1>;
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status = "disabled";
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label = "SPI_0";
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};
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spi1: spi@40004000 {
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compatible = "nordic,nrf-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40004000 0x1000>;
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interrupts = <4 1>;
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status = "disabled";
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label = "SPI_1";
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};
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wdt: watchdog@40010000 {
|
||||
compatible = "nordic,nrf-watchdog";
|
||||
reg = <0x40010000 0x1000>;
|
||||
|
|
|
@ -85,6 +85,16 @@
|
|||
label = "I2C_0";
|
||||
};
|
||||
|
||||
spi0: spi@40004000 {
|
||||
compatible = "nordic,nrf-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40004000 0x1000>;
|
||||
interrupts = <4 1>;
|
||||
status = "disabled";
|
||||
label = "SPI_0";
|
||||
};
|
||||
|
||||
wdt: watchdog@40010000 {
|
||||
compatible = "nordic,nrf-watchdog";
|
||||
reg = <0x40010000 0x1000>;
|
||||
|
|
|
@ -97,6 +97,36 @@
|
|||
label = "I2C_1";
|
||||
};
|
||||
|
||||
spi0: spi@40003000 {
|
||||
compatible = "nordic,nrf-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003000 0x1000>;
|
||||
interrupts = <3 1>;
|
||||
status = "disabled";
|
||||
label = "SPI_0";
|
||||
};
|
||||
|
||||
spi1: spi@40004000 {
|
||||
compatible = "nordic,nrf-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40004000 0x1000>;
|
||||
interrupts = <4 1>;
|
||||
status = "disabled";
|
||||
label = "SPI_1";
|
||||
};
|
||||
|
||||
spi2: spi@40023000 {
|
||||
compatible = "nordic,nrf-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40023000 0x1000>;
|
||||
interrupts = <35 1>;
|
||||
status = "disabled";
|
||||
label = "SPI_2";
|
||||
};
|
||||
|
||||
wdt: watchdog@40010000 {
|
||||
compatible = "nordic,nrf-watchdog";
|
||||
reg = <0x40010000 0x1000>;
|
||||
|
|
|
@ -116,6 +116,46 @@
|
|||
label = "I2C_1";
|
||||
};
|
||||
|
||||
spi0: spi@40003000 {
|
||||
compatible = "nordic,nrf-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003000 0x1000>;
|
||||
interrupts = <3 1>;
|
||||
status = "disabled";
|
||||
label = "SPI_0";
|
||||
};
|
||||
|
||||
spi1: spi@40004000 {
|
||||
compatible = "nordic,nrf-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40004000 0x1000>;
|
||||
interrupts = <4 1>;
|
||||
status = "disabled";
|
||||
label = "SPI_1";
|
||||
};
|
||||
|
||||
spi2: spi@40023000 {
|
||||
compatible = "nordic,nrf-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40023000 0x1000>;
|
||||
interrupts = <35 1>;
|
||||
status = "disabled";
|
||||
label = "SPI_2";
|
||||
};
|
||||
|
||||
spi3: spi@4002B000 {
|
||||
compatible = "nordic,nrf-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x4002B000 0x1000>;
|
||||
interrupts = <47 1>;
|
||||
status = "disabled";
|
||||
label = "SPI_3";
|
||||
};
|
||||
|
||||
usbd: usbd@40027000 {
|
||||
compatible = "nordic,nrf-usbd";
|
||||
reg = <0x40027000 0x1000>;
|
||||
|
|
60
dts/bindings/spi/nordic,nrf-spi.yaml
Normal file
60
dts/bindings/spi/nordic,nrf-spi.yaml
Normal file
|
@ -0,0 +1,60 @@
|
|||
#
|
||||
# Copyright (c) 2018 Nordic Semiconductor ASA
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-5-Clause-Nordic
|
||||
#
|
||||
---
|
||||
title: Nordic nRF Family SPI Master node
|
||||
id: nordic,nrf-spi
|
||||
version: 0.1
|
||||
|
||||
description: >
|
||||
This is a representation of the Nordic nRF SPI node
|
||||
|
||||
inherits:
|
||||
!include spi.yaml
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
type: string
|
||||
category: required
|
||||
description: compatible strings
|
||||
constraint: "nordic,nrf-spi"
|
||||
|
||||
reg:
|
||||
type: array
|
||||
description: mmio register space
|
||||
generation: define
|
||||
category: required
|
||||
|
||||
interrupts:
|
||||
type: array
|
||||
category: required
|
||||
description: required interrupts
|
||||
generation: define
|
||||
|
||||
sck-pin:
|
||||
type: int
|
||||
description: SCK pin
|
||||
generation: define
|
||||
category: required
|
||||
|
||||
mosi-pin:
|
||||
type: int
|
||||
description: MOSI pin
|
||||
generation: define
|
||||
category: required
|
||||
|
||||
miso-pin:
|
||||
type: int
|
||||
description: MISO pin
|
||||
generation: define
|
||||
category: required
|
||||
|
||||
csn-pin:
|
||||
type: int
|
||||
description: CSN pin
|
||||
generation: define
|
||||
category: optional
|
||||
|
||||
...
|
|
@ -1,12 +1,8 @@
|
|||
CONFIG_SPI_NRFX=y
|
||||
CONFIG_SPI_0=y
|
||||
CONFIG_SPI_0_IRQ_PRI=1
|
||||
CONFIG_SPI_0_NRF_SPI=y
|
||||
CONFIG_SPI_0_NRF_SCK_PIN=4
|
||||
CONFIG_SPI_0_NRF_MOSI_PIN=6
|
||||
CONFIG_SPI_0_NRF_MISO_PIN=5
|
||||
|
||||
CONFIG_SPI_LOOPBACK_DRV_NAME="SPI_0"
|
||||
CONFIG_SPI_LOOPBACK_CS_GPIO=y
|
||||
CONFIG_SPI_LOOPBACK_CS_CTRL_GPIO_DRV_NAME="GPIO_0"
|
||||
CONFIG_SPI_LOOPBACK_CS_CTRL_GPIO_PIN=30
|
||||
CONFIG_SPI_LOOPBACK_CS_CTRL_GPIO_PIN=28
|
||||
|
|
|
@ -1,14 +1,10 @@
|
|||
CONFIG_SPI_NRFX=y
|
||||
CONFIG_SPI_NRFX_RAM_BUFFER_SIZE=8
|
||||
CONFIG_SPI_3=y
|
||||
CONFIG_SPI_3_IRQ_PRI=1
|
||||
CONFIG_SPI_3_NRF_SPIM=y
|
||||
CONFIG_SPI_3_NRF_SCK_PIN=29
|
||||
CONFIG_SPI_3_NRF_MOSI_PIN=31
|
||||
CONFIG_SPI_3_NRF_MISO_PIN=30
|
||||
CONFIG_SPI_3_NRF_RX_DELAY=1
|
||||
|
||||
CONFIG_SPI_LOOPBACK_DRV_NAME="SPI_3"
|
||||
CONFIG_SPI_LOOPBACK_CS_GPIO=y
|
||||
CONFIG_SPI_LOOPBACK_CS_CTRL_GPIO_DRV_NAME="GPIO_0"
|
||||
CONFIG_SPI_LOOPBACK_CS_CTRL_GPIO_PIN=26
|
||||
CONFIG_SPI_LOOPBACK_CS_CTRL_GPIO_PIN=28
|
||||
|
|
|
@ -1,12 +1,8 @@
|
|||
CONFIG_SPI_NRFX=y
|
||||
CONFIG_SPI_1=y
|
||||
CONFIG_SPI_1_IRQ_PRI=1
|
||||
CONFIG_SPI_1_NRF_SPI=y
|
||||
CONFIG_SPI_1_NRF_SCK_PIN=29
|
||||
CONFIG_SPI_1_NRF_MOSI_PIN=31
|
||||
CONFIG_SPI_1_NRF_MISO_PIN=30
|
||||
|
||||
CONFIG_SPI_LOOPBACK_DRV_NAME="SPI_1"
|
||||
CONFIG_SPI_LOOPBACK_CS_GPIO=y
|
||||
CONFIG_SPI_LOOPBACK_CS_CTRL_GPIO_DRV_NAME="GPIO_0"
|
||||
CONFIG_SPI_LOOPBACK_CS_CTRL_GPIO_PIN=26
|
||||
CONFIG_SPI_LOOPBACK_CS_CTRL_GPIO_PIN=28
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue