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dts: Add cpus and cpu nodes missing properties

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This patch adds #address-cell, #size-cell properties to
cpus container node and device_type, reg properties to
cpu node.

Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
This commit is contained in:
Yannis Damigos 2017-07-15 21:57:32 +03:00 • committed by Kumar Gala
commit 941ffb017b
23 changed files with 187 additions and 16 deletions
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5
dts/arm/atmel/sam3x.dtsi
View file

@ -8,8 +8,13 @@
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m4";
reg = <0>;
};
};

5
dts/arm/atmel/sam4s.dtsi
View file

@ -8,8 +8,13 @@
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m4";
reg = <0>;
};
};

5
dts/arm/atmel/same70.dtsi
View file

@ -10,8 +10,13 @@
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m7";
reg = <0>;
};
};

5
dts/arm/nordic/nrf51822.dtsi
View file

@ -3,8 +3,13 @@
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m0";
reg = <0>;
};
};

5
dts/arm/nordic/nrf52832.dtsi
View file

@ -3,8 +3,13 @@
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m4f";
reg = <0>;
};
};

5
dts/arm/nordic/nrf52840.dtsi
View file

@ -3,8 +3,13 @@
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m4f";
reg = <0>;
};
};

5
dts/arm/nxp/nxp_k6x.dtsi
View file

@ -2,8 +2,13 @@
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m4f";
reg = <0>;
};
};

5
dts/arm/nxp/nxp_kl25z.dtsi
View file

@ -2,8 +2,13 @@
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m0+";
reg = <0>;
};
};

5
dts/arm/nxp/nxp_kw40z.dtsi
View file

@ -2,8 +2,13 @@
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m0+";
reg = <0>;
};
};

5
dts/arm/nxp/nxp_kw41z.dtsi
View file

@ -2,8 +2,13 @@
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m0+";
reg = <0>;
};
};

11
dts/arm/st/stm32f103Xb.dtsi
View file

@ -11,6 +11,17 @@
#include <st/mem.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m3";
reg = <0>;
};
};
flash0: flash {
reg = <0x08000000 DT_FLASH_SIZE>;
};

11
dts/arm/st/stm32f103Xe.dtsi
View file

@ -11,6 +11,17 @@
#include <st/mem.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m3";
reg = <0>;
};
};
flash0: flash {
reg = <0x08000000 DT_FLASH_SIZE>;
};

11
dts/arm/st/stm32f107.dtsi
View file

@ -8,6 +8,17 @@
#include <st/mem.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m3";
reg = <0>;
};
};
flash0: flash {
reg = <0x08000000 DT_FLASH_SIZE>;
};

11
dts/arm/st/stm32f303.dtsi
View file

@ -8,6 +8,17 @@
#include <st/mem.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m4f";
reg = <0>;
};
};
flash0: flash {
reg = <0x08000000 DT_FLASH_SIZE>;
};

11
dts/arm/st/stm32f334.dtsi
View file

@ -8,6 +8,17 @@
#include <st/mem.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m4f";
reg = <0>;
};
};
flash0: flash {
reg = <0x08000000 DT_FLASH_SIZE>;
};

11
dts/arm/st/stm32f373.dtsi
View file

@ -8,6 +8,17 @@
#include <st/mem.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m4f";
reg = <0>;
};
};
flash0: flash {
reg = <0x08000000 DT_FLASH_SIZE>;
};

11
dts/arm/st/stm32f4.dtsi
View file

@ -8,6 +8,17 @@
#include <st/mem.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m4f";
reg = <0>;
};
};
flash0: flash {
reg = <0x08000000 DT_FLASH_SIZE>;
};

11
dts/arm/st/stm32l432.dtsi
View file

@ -8,6 +8,17 @@
#include <st/mem.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m4f";
reg = <0>;
};
};
flash0: flash {
reg = <0x08000000 DT_FLASH_SIZE>;
};

11
dts/arm/st/stm32l475.dtsi
View file

@ -8,6 +8,17 @@
#include <st/mem.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m4f";
reg = <0>;
};
};
flash0: flash {
reg = <0x08000000 DT_FLASH_SIZE>;
};

37
dts/arm/ti/cc2650.dtsi
View file

@ -7,23 +7,28 @@
#include "armv7-m.dtsi"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m3";
reg = <0>;
};
};
sram0: memory {
compatible = "sram";
reg = <0x20000000 0x5000>;
};
flash0: serial-flash {
compatible = "serial-flash";
reg = <0x0 0x20000>;
};
soc {
cpus {
cpu@0 {
compatible = "arm,cortex-m3";
};
};
sram0: memory {
compatible = "sram";
reg = <0x20000000 0x5000>;
};
flash0: serial-flash {
compatible = "serial-flash";
reg = <0x0 0x20000>;
};
gpioa: gpio@40022000 {
compatible = "ti,cc2650-gpio";
reg = <0x40022000 0xE4>;

5
dts/arm/ti/cc32xx.dtsi
View file

@ -9,8 +9,13 @@
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m4";
reg = <0>;
};
};

5
dts/arm/ti/lm3s6965.dtsi
View file

@ -2,8 +2,13 @@
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m3";
reg = <0>;
};
};

7
dts/x86/intel_curie.dtsi
View file

@ -3,12 +3,19 @@
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "intel,quark";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arc";
reg = <1>;
};
};