arch: arm: lpc: Added support for Cortex-M0+ on lpc54114 soc
Add soc configuration support and dts files for nxp_lpc54xxx_m0. Adjusted nxp_lpc54xxx soc, configuration and dts files for the presence of slave core. Origin: Original Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
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6 changed files with 76 additions and 0 deletions
39
arch/arm/soc/nxp_lpc/lpc54xxx/Kconfig.defconfig.lpc54114_m0
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arch/arm/soc/nxp_lpc/lpc54xxx/Kconfig.defconfig.lpc54114_m0
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@ -0,0 +1,39 @@
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# Kconfig - NXP LPC54114 M0 platform configuration options
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#
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# Copyright (c) 2017, NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_LPC54114_M0
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config SOC
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string
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default lpc54114_m0
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if PINMUX
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config PINMUX_MCUX_LPC
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def_bool n
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endif # PINMUX
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config GPIO
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def_bool n
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if GPIO
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config GPIO_MCUX_LPC
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def_bool n
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endif # GPIO
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if SERIAL
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config USART_MCUX_LPC
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def_bool n
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endif # SERIAL
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endif # SOC_LPC54114_M0
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@ -14,6 +14,11 @@ config SOC_LPC54114_M4
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select CPU_CORTEX_M4
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select PLATFORM_SPECIFIC_INIT
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config SOC_LPC54114_M0
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bool "SOC_LPC54114_M0"
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select CPU_CORTEX_M0PLUS
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select CPU_CORTEX_M_HAS_VTOR
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endchoice
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if SOC_SERIES_LPC54XXX
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@ -6,7 +6,11 @@
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/* SoC level DTS fixup file */
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#if defined(CONFIG_SOC_LPC54114_M0)
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#else
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#endif
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#define CONFIG_USART_MCUX_LPC_0_BASE_ADDRESS NXP_LPC_USART_40086000_BASE_ADDRESS
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#define CONFIG_USART_MCUX_LPC_0_BAUD_RATE NXP_LPC_USART_40086000_CURRENT_SPEED
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@ -35,6 +35,8 @@
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static ALWAYS_INLINE void clkInit(void)
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{
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#ifdef CONFIG_SOC_LPC54114_M4
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/* Set up the clock sources */
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/* Ensure FRO is on */
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@ -62,6 +64,7 @@ static ALWAYS_INLINE void clkInit(void)
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/* Attach 12 MHz clock to FLEXCOMM0 */
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CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);
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#endif /* CONFIG_SOC_LPC54114_M4 */
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}
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/**
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22
dts/arm/nxp/nxp_lpc54xxx_m0.dtsi
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dts/arm/nxp/nxp_lpc54xxx_m0.dtsi
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/*
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* Copyright (c) 2017, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv6-m.dtsi>
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#include <nxp/nxp_lpc54xxx.dtsi>
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/ {
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cpus {
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/delete-node/ cpu@0;
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cpu@1 {
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compatible = "arm,cortex-m0+";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <2>;
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};
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@ -4,6 +4,9 @@ string(TOUPPER ${CONFIG_SOC} MCUX_DEVICE)
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if("${MCUX_DEVICE}" STREQUAL "LPC54114")
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set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm4)
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elseif("${MCUX_DEVICE}" STREQUAL "LPC54114_M0")
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set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm0plus)
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set(MCUX_DEVICE LPC54114)
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else()
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set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER})
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endif()
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