drivers: i2s: change the stm32 DMA in the driver to use dts
This commit moves DMA parameters previously hard coded in the driver to the dts. Signed-off-by: Song Qiang <songqiang1304521@gmail.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Song Qiang
Kumar Gala
parent
9561785ea7
commit
f0d3ee52fb
8 changed files with 149 additions and 45 deletions
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@ -7,6 +7,7 @@
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#include <string.h>
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#include <drivers/dma.h>
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#include <drivers/i2s.h>
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#include <dt-bindings/dma/stm32_dma.h>
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#include <soc.h>
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#include <clock_control/stm32_clock_control.h>
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#include <drivers/clock_control.h>
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@ -838,23 +839,29 @@ static struct device *get_dev_from_tx_dma_channel(u32_t dma_channel)
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return active_dma_tx_channel[dma_channel];
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}
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#define I2S_DMA_CHANNEL_INIT(index, dir, dir_cap) \
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/* src_dev and dest_dev should be 'MEM' or 'PERIPH'. */
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#define I2S_DMA_CHANNEL_INIT(index, dir, dir_cap, src_dev, dest_dev) \
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.dir = { \
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.dma_channel = I2S##index##_DMA_CHAN_##dir_cap, \
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.dma_name = DT_I2S_##index##_DMA_CONTROLLER_##dir_cap, \
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.dma_channel = DT_I2S_##index##_DMA_CHANNEL_##dir_cap, \
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.dma_cfg = { \
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.block_count = 1, \
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.dma_slot = I2S##index##_DMA_SLOT_##dir_cap, \
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.dma_slot = DT_I2S_##index##_DMA_SLOT_##dir_cap, \
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.channel_direction = PERIPHERAL_TO_MEMORY, \
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.source_data_size = 1, /* 16bit default */ \
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.dest_data_size = 1, /* 16bit default */ \
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.source_burst_length = 0, /* SINGLE transfer */ \
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.dest_burst_length = 1, \
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.channel_priority = I2S_DMA_CHAN_PRIORITY, \
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.channel_priority = STM32_DMA_CONFIG_PRIORITY( \
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DT_I2S_##index##_DMA_CHANNEL_CONFIG_##dir_cap), \
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.dma_callback = dma_##dir##_callback, \
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}, \
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.src_addr_increment = I2S_DMA_SRC_ADDR_INC_##dir_cap, \
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.dst_addr_increment = I2S_DMA_DST_ADDR_INC_##dir_cap, \
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.fifo_threshold = I2S_DMA_FIFO_THRESHOLD, \
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.src_addr_increment = STM32_DMA_CONFIG_##src_dev##_ADDR_INC( \
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DT_I2S_##index##_DMA_CHANNEL_CONFIG_##dir_cap), \
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.dst_addr_increment = STM32_DMA_CONFIG_##dest_dev##_ADDR_INC( \
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DT_I2S_##index##_DMA_CHANNEL_CONFIG_##dir_cap), \
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.fifo_threshold = STM32_DMA_FEATURES_FIFO_THRESHOLD( \
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DT_I2S_##index##_DMA_FEATURES_##dir_cap), \
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.stream_start = dir##_stream_start, \
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.stream_disable = dir##_stream_disable, \
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.queue_drop = dir##_queue_drop, \
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@ -881,9 +888,8 @@ struct queue_item rx_##index##_ring_buf[CONFIG_I2S_STM32_RX_BLOCK_COUNT + 1];\
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struct queue_item tx_##index##_ring_buf[CONFIG_I2S_STM32_TX_BLOCK_COUNT + 1];\
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\
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static struct i2s_stm32_data i2s_stm32_data_##index = { \
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.dma_name = I2S##index##_DMA_CHAN_RX, \
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I2S_DMA_CHANNEL_INIT(index, rx, RX), \
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I2S_DMA_CHANNEL_INIT(index, tx, TX), \
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I2S_DMA_CHANNEL_INIT(index, rx, RX, PERIPH, MEM), \
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I2S_DMA_CHANNEL_INIT(index, tx, TX, MEM, PERIPH), \
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}; \
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DEVICE_AND_API_INIT(i2s_stm32_##index, DT_I2S_##index##_NAME, \
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&i2s_stm32_initialize, &i2s_stm32_data_##index, \
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@ -49,40 +49,6 @@
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#endif /* CONFIG_I2S_STM32_USE_PLLI2S_ENABLE */
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#ifdef CONFIG_SOC_SERIES_STM32F4X
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#define I2S1_DMA_NAME CONFIG_DMA_2_NAME
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#define I2S1_DMA_CHAN_RX 2
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#define I2S1_DMA_SLOT_RX 3
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#define I2S1_DMA_CHAN_TX 3
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#define I2S1_DMA_SLOT_TX 3
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#define I2S2_DMA_NAME CONFIG_DMA_1_NAME
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#define I2S2_DMA_CHAN_RX 3
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#define I2S2_DMA_SLOT_RX 0
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#define I2S2_DMA_CHAN_TX 4
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#define I2S2_DMA_SLOT_TX 0
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#define I2S3_DMA_NAME CONFIG_DMA_1_NAME
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#define I2S3_DMA_CHAN_RX 0
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#define I2S3_DMA_SLOT_RX 0
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#define I2S3_DMA_CHAN_TX 5
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#define I2S3_DMA_SLOT_TX 0
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#define I2S4_DMA_NAME CONFIG_DMA_2_NAME
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#define I2S4_DMA_CHAN_RX 0
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#define I2S4_DMA_SLOT_RX 4
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#define I2S4_DMA_CHAN_TX 1
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#define I2S4_DMA_SLOT_TX 4
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#define I2S5_DMA_NAME CONFIG_DMA_2_NAME
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#define I2S5_DMA_CHAN_RX 5
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#define I2S5_DMA_SLOT_RX 7
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#define I2S5_DMA_CHAN_TX 6
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#define I2S5_DMA_SLOT_TX 7
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#define I2S_DMA_SRC_ADDR_INC_RX 0
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#define I2S_DMA_DST_ADDR_INC_RX 1
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#define I2S_DMA_SRC_ADDR_INC_TX 1
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#define I2S_DMA_DST_ADDR_INC_TX 0
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#define I2S_DMA_FIFO_THRESHOLD 3 /* Full FIFO */
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#define I2S_DMA_CHAN_PRIORITY 0
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#endif
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#define DEV_CFG(dev) \
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(const struct i2s_stm32_cfg * const)((dev)->config->config_info)
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#define DEV_DATA(dev) \
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@ -112,6 +78,8 @@ struct i2s_stm32_cfg {
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struct stream {
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s32_t state;
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struct k_sem sem;
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const char *dma_name;
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u32_t dma_channel;
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struct dma_config dma_cfg;
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u8_t priority;
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@ -213,6 +213,9 @@
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reg = <0x40013000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
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interrupts = <35 5>;
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dmas = <&dma2 3 3 0x400 0x3
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&dma2 2 3 0x400 0x3>;
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dma-names = "tx", "rx";
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status = "disabled";
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label = "I2S_1";
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};
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@ -37,6 +37,9 @@
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reg = <0x40003800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
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interrupts = <36 5>;
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dmas = <&dma1 4 0 0x400 0x3
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&dma1 3 0 0x400 0x3>;
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dma-names = "tx", "rx";
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status = "disabled";
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label = "I2S_2";
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};
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@ -48,6 +51,9 @@
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reg = <0x40003c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
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interrupts = <51 5>;
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dmas = <&dma1 5 0 0x400 0x3
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&dma1 0 0 0x400 0x3>;
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dma-names = "tx", "rx";
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status = "disabled";
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label = "I2S_3";
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};
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@ -35,6 +35,9 @@
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reg = <0x40013400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
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interrupts = <84 5>;
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dmas = <&dma2 1 4 0x400 0x3
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&dma2 0 4 0x400 0x3>;
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dma-names = "tx", "rx";
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status = "disabled";
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label = "I2S_4";
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};
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@ -46,6 +49,9 @@
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reg = <0x40015000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
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interrupts = <85 5>;
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dmas = <&dma2 6 7 0x400 0x3
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&dma2 5 7 0x400 0x3>;
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dma-names = "tx", "rx";
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status = "disabled";
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label = "I2S_5";
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};
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16
dts/bindings/dma/dma.yaml
Normal file
16
dts/bindings/dma/dma.yaml
Normal file
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@ -0,0 +1,16 @@
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# Copyright (c) 2019, Linaro Limited
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# Copyright (c) 2019, Song Qiang <songqiang1304521@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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# Common fields for DMA users
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properties:
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dmas:
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required: true
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type: phandle-array
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description: DMA instances information
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dma-names:
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required: false
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type: string-array
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description: name of each dma instance
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@ -8,7 +8,7 @@ description: |
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compatible: "st,stm32-i2s"
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include: i2s-controller.yaml
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include: [i2s-controller.yaml, dma.yaml]
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properties:
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reg:
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@ -16,3 +16,6 @@ properties:
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interrupts:
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required: true
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dma-names:
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required: true
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@ -244,6 +244,22 @@
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#define DT_I2S_1_IRQ DT_ST_STM32_I2S_40013000_IRQ_0
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#define DT_I2S_1_CLOCK_BITS DT_ST_STM32_I2S_40013000_CLOCK_BITS
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#define DT_I2S_1_CLOCK_BUS DT_ST_STM32_I2S_40013000_CLOCK_BUS
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#define DT_I2S_1_DMA_CONTROLLER_TX \
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DT_ST_STM32_I2S_40013000_TX_DMAS_CONTROLLER
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#define DT_I2S_1_DMA_CHANNEL_TX DT_ST_STM32_I2S_40013000_TX_DMAS_CHANNEL
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#define DT_I2S_1_DMA_SLOT_TX DT_ST_STM32_I2S_40013000_TX_DMAS_SLOT
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#define DT_I2S_1_DMA_CHANNEL_CONFIG_TX \
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DT_ST_STM32_I2S_40013000_TX_DMAS_CHANNEL_CONFIG
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#define DT_I2S_1_DMA_FEATURES_TX \
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DT_ST_STM32_I2S_40013000_TX_DMAS_FEATURES
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#define DT_I2S_1_DMA_CONTROLLER_RX \
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DT_ST_STM32_I2S_40013000_RX_DMAS_CONTROLLER
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#define DT_I2S_1_DMA_CHANNEL_RX DT_ST_STM32_I2S_40013000_RX_DMAS_CHANNEL
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#define DT_I2S_1_DMA_SLOT_RX DT_ST_STM32_I2S_40013000_RX_DMAS_SLOT
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#define DT_I2S_1_DMA_CHANNEL_CONFIG_RX \
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DT_ST_STM32_I2S_40013000_RX_DMAS_CHANNEL_CONFIG
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#define DT_I2S_1_DMA_FEATURES_RX \
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DT_ST_STM32_I2S_40013000_RX_DMAS_FEATURES
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#define DT_I2S_2_BASE_ADDRESS DT_ST_STM32_I2S_40003800_BASE_ADDRESS
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#define DT_I2S_2_IRQ_PRI DT_ST_STM32_I2S_40003800_IRQ_0_PRIORITY
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@ -251,6 +267,22 @@
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#define DT_I2S_2_IRQ DT_ST_STM32_I2S_40003800_IRQ_0
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#define DT_I2S_2_CLOCK_BITS DT_ST_STM32_I2S_40003800_CLOCK_BITS
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#define DT_I2S_2_CLOCK_BUS DT_ST_STM32_I2S_40003800_CLOCK_BUS
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#define DT_I2S_2_DMA_CONTROLLER_TX \
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DT_ST_STM32_I2S_40003800_TX_DMAS_CONTROLLER
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#define DT_I2S_2_DMA_CHANNEL_TX DT_ST_STM32_I2S_40003800_TX_DMAS_CHANNEL
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#define DT_I2S_2_DMA_SLOT_TX DT_ST_STM32_I2S_40003800_TX_DMAS_SLOT
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#define DT_I2S_2_DMA_CHANNEL_CONFIG_TX \
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DT_ST_STM32_I2S_40003800_TX_DMAS_CHANNEL_CONFIG
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#define DT_I2S_2_DMA_FEATURES_TX \
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DT_ST_STM32_I2S_40003800_TX_DMAS_FEATURES
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#define DT_I2S_2_DMA_CONTROLLER_RX \
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DT_ST_STM32_I2S_40003800_RX_DMAS_CONTROLLER
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#define DT_I2S_2_DMA_CHANNEL_RX DT_ST_STM32_I2S_40003800_RX_DMAS_CHANNEL
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#define DT_I2S_2_DMA_SLOT_RX DT_ST_STM32_I2S_40003800_RX_DMAS_SLOT
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#define DT_I2S_2_DMA_CHANNEL_CONFIG_RX \
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DT_ST_STM32_I2S_40003800_RX_DMAS_CHANNEL_CONFIG
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#define DT_I2S_2_DMA_FEATURES_RX \
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DT_ST_STM32_I2S_40003800_RX_DMAS_FEATURES
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#define DT_I2S_3_BASE_ADDRESS DT_ST_STM32_I2S_40003C00_BASE_ADDRESS
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#define DT_I2S_3_IRQ_PRI DT_ST_STM32_I2S_40003C00_IRQ_0_PRIORITY
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@ -258,6 +290,22 @@
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#define DT_I2S_3_IRQ DT_ST_STM32_I2S_40003C00_IRQ_0
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#define DT_I2S_3_CLOCK_BITS DT_ST_STM32_I2S_40003C00_CLOCK_BITS
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#define DT_I2S_3_CLOCK_BUS DT_ST_STM32_I2S_40003C00_CLOCK_BUS
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#define DT_I2S_3_DMA_CONTROLLER_TX \
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DT_ST_STM32_I2S_40003C00_TX_DMAS_CONTROLLER
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#define DT_I2S_3_DMA_CHANNEL_TX DT_ST_STM32_I2S_40003C00_TX_DMAS_CHANNEL
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#define DT_I2S_3_DMA_SLOT_TX DT_ST_STM32_I2S_40003C00_TX_DMAS_SLOT
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#define DT_I2S_3_DMA_CHANNEL_CONFIG_TX \
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DT_ST_STM32_I2S_40003C00_TX_DMAS_CHANNEL_CONFIG
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#define DT_I2S_3_DMA_FEATURES_TX \
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DT_ST_STM32_I2S_40003C00_TX_DMAS_FEATURES
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#define DT_I2S_3_DMA_CONTROLLER_RX \
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DT_ST_STM32_I2S_40003C00_RX_DMAS_CONTROLLER
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#define DT_I2S_3_DMA_CHANNEL_RX DT_ST_STM32_I2S_40003C00_RX_DMAS_CHANNEL
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#define DT_I2S_3_DMA_SLOT_RX DT_ST_STM32_I2S_40003C00_RX_DMAS_SLOT
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#define DT_I2S_3_DMA_CHANNEL_CONFIG_RX \
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DT_ST_STM32_I2S_40003C00_RX_DMAS_CHANNEL_CONFIG
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#define DT_I2S_3_DMA_FEATURES_RX \
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DT_ST_STM32_I2S_40003C00_RX_DMAS_FEATURES
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#define DT_I2S_4_BASE_ADDRESS DT_ST_STM32_I2S_40013400_BASE_ADDRESS
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#define DT_I2S_4_IRQ_PRI DT_ST_STM32_I2S_40013400_IRQ_0_PRIORITY
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@ -265,6 +313,22 @@
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#define DT_I2S_4_IRQ DT_ST_STM32_I2S_40013400_IRQ_0
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#define DT_I2S_4_CLOCK_BITS DT_ST_STM32_I2S_40013400_CLOCK_BITS
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#define DT_I2S_4_CLOCK_BUS DT_ST_STM32_I2S_40013400_CLOCK_BUS
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#define DT_I2S_4_DMA_CONTROLLER_TX \
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DT_ST_STM32_I2S_40013400_TX_DMAS_CONTROLLER
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#define DT_I2S_4_DMA_CHANNEL_TX DT_ST_STM32_I2S_40013400_TX_DMAS_CHANNEL
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#define DT_I2S_4_DMA_SLOT_TX DT_ST_STM32_I2S_40013400_TX_DMAS_SLOT
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#define DT_I2S_4_DMA_CHANNEL_CONFIG_TX \
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DT_ST_STM32_I2S_40013400_TX_DMAS_CHANNEL_CONFIG
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#define DT_I2S_4_DMA_FEATURES_TX \
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DT_ST_STM32_I2S_40013400_TX_DMAS_FEATURES
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#define DT_I2S_4_DMA_CONTROLLER_RX \
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DT_ST_STM32_I2S_40013400_RX_DMAS_CONTROLLER
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#define DT_I2S_4_DMA_CHANNEL_RX DT_ST_STM32_I2S_40013400_RX_DMAS_CHANNEL
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#define DT_I2S_4_DMA_SLOT_RX DT_ST_STM32_I2S_40013400_RX_DMAS_SLOT
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#define DT_I2S_4_DMA_CHANNEL_CONFIG_RX \
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DT_ST_STM32_I2S_40013400_RX_DMAS_CHANNEL_CONFIG
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#define DT_I2S_4_DMA_FEATURES_RX \
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DT_ST_STM32_I2S_40013400_RX_DMAS_FEATURES
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#define DT_I2S_5_BASE_ADDRESS DT_ST_STM32_I2S_40015000_BASE_ADDRESS
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#define DT_I2S_5_IRQ_PRI DT_ST_STM32_I2S_40015000_IRQ_0_PRIORITY
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#define DT_I2S_5_IRQ DT_ST_STM32_I2S_40015000_IRQ_0
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#define DT_I2S_5_CLOCK_BITS DT_ST_STM32_I2S_40015000_CLOCK_BITS
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#define DT_I2S_5_CLOCK_BUS DT_ST_STM32_I2S_40015000_CLOCK_BUS
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#define DT_I2S_5_DMA_CONTROLLER_TX \
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DT_ST_STM32_I2S_40015000_TX_DMAS_CONTROLLER
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#define DT_I2S_5_DMA_CHANNEL_TX DT_ST_STM32_I2S_40015000_TX_DMAS_CHANNEL
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#define DT_I2S_5_DMA_SLOT_TX DT_ST_STM32_I2S_40015000_TX_DMAS_SLOT
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#define DT_I2S_5_DMA_CHANNEL_CONFIG_TX \
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DT_ST_STM32_I2S_40015000_TX_DMAS_CHANNEL_CONFIG
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#define DT_I2S_5_DMA_FEATURES_TX \
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DT_ST_STM32_I2S_40015000_TX_DMAS_FEATURES
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#define DT_I2S_5_DMA_CONTROLLER_RX \
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DT_ST_STM32_I2S_40015000_RX_DMAS_CONTROLLER
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#define DT_I2S_5_DMA_CHANNEL_RX DT_ST_STM32_I2S_40015000_RX_DMAS_CHANNEL
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#define DT_I2S_5_DMA_SLOT_RX DT_ST_STM32_I2S_40015000_RX_DMAS_SLOT
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#define DT_I2S_5_DMA_CHANNEL_CONFIG_RX \
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DT_ST_STM32_I2S_40015000_RX_DMAS_CHANNEL_CONFIG
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#define DT_I2S_5_DMA_FEATURES_RX \
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DT_ST_STM32_I2S_40015000_RX_DMAS_FEATURES
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#define DT_I2S_6_BASE_ADDRESS DT_ST_STM32_I2S_40015400_BASE_ADDRESS
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#define DT_I2S_6_IRQ_PRI DT_ST_STM32_I2S_40015400_IRQ_0_PRIORITY
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@ -279,6 +359,22 @@
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#define DT_I2S_6_IRQ DT_ST_STM32_I2S_40015400_IRQ_0
|
||||
#define DT_I2S_6_CLOCK_BITS DT_ST_STM32_I2S_40015400_CLOCK_BITS
|
||||
#define DT_I2S_6_CLOCK_BUS DT_ST_STM32_I2S_40015400_CLOCK_BUS
|
||||
#define DT_I2S_6_DMA_CONTROLLER_TX \
|
||||
DT_ST_STM32_I2S_40015400_TX_DMAS_CONTROLLER
|
||||
#define DT_I2S_6_DMA_CHANNEL_TX DT_ST_STM32_I2S_40015400_TX_DMAS_CHANNEL
|
||||
#define DT_I2S_6_DMA_SLOT_TX DT_ST_STM32_I2S_40015400_TX_DMAS_SLOT
|
||||
#define DT_I2S_6_DMA_CHANNEL_CONFIG_TX \
|
||||
DT_ST_STM32_I2S_40015400_TX_DMAS_CHANNEL_CONFIG
|
||||
#define DT_I2S_6_DMA_FEATURES_TX \
|
||||
DT_ST_STM32_I2S_40015400_TX_DMAS_FEATURES
|
||||
#define DT_I2S_6_DMA_CONTROLLER_RX \
|
||||
DT_ST_STM32_I2S_40015400_RX_DMAS_CONTROLLER
|
||||
#define DT_I2S_6_DMA_CHANNEL_RX DT_ST_STM32_I2S_40015400_RX_DMAS_CHANNEL
|
||||
#define DT_I2S_6_DMA_SLOT_RX DT_ST_STM32_I2S_40015400_RX_DMAS_SLOT
|
||||
#define DT_I2S_6_DMA_CHANNEL_CONFIG_RX \
|
||||
DT_ST_STM32_I2S_40015400_RX_DMAS_CHANNEL_CONFIG
|
||||
#define DT_I2S_6_DMA_FEATURES_RX \
|
||||
DT_ST_STM32_I2S_40015400_RX_DMAS_FEATURES
|
||||
|
||||
#define DT_FLASH_DEV_BASE_ADDRESS DT_ST_STM32F4_FLASH_CONTROLLER_40023C00_BASE_ADDRESS
|
||||
#define DT_FLASH_DEV_NAME DT_ST_STM32F4_FLASH_CONTROLLER_40023C00_LABEL
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue