drivers: i2s: change the stm32 DMA in the driver to use dts

This commit moves DMA parameters previously hard coded in the driver
to the dts.

Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Song Qiang 2019-10-24 15:57:17 +08:00 committed by Kumar Gala
commit f0d3ee52fb
8 changed files with 149 additions and 45 deletions

View file

@ -7,6 +7,7 @@
#include <string.h>
#include <drivers/dma.h>
#include <drivers/i2s.h>
#include <dt-bindings/dma/stm32_dma.h>
#include <soc.h>
#include <clock_control/stm32_clock_control.h>
#include <drivers/clock_control.h>
@ -838,23 +839,29 @@ static struct device *get_dev_from_tx_dma_channel(u32_t dma_channel)
return active_dma_tx_channel[dma_channel];
}
#define I2S_DMA_CHANNEL_INIT(index, dir, dir_cap) \
/* src_dev and dest_dev should be 'MEM' or 'PERIPH'. */
#define I2S_DMA_CHANNEL_INIT(index, dir, dir_cap, src_dev, dest_dev) \
.dir = { \
.dma_channel = I2S##index##_DMA_CHAN_##dir_cap, \
.dma_name = DT_I2S_##index##_DMA_CONTROLLER_##dir_cap, \
.dma_channel = DT_I2S_##index##_DMA_CHANNEL_##dir_cap, \
.dma_cfg = { \
.block_count = 1, \
.dma_slot = I2S##index##_DMA_SLOT_##dir_cap, \
.dma_slot = DT_I2S_##index##_DMA_SLOT_##dir_cap, \
.channel_direction = PERIPHERAL_TO_MEMORY, \
.source_data_size = 1, /* 16bit default */ \
.dest_data_size = 1, /* 16bit default */ \
.source_burst_length = 0, /* SINGLE transfer */ \
.dest_burst_length = 1, \
.channel_priority = I2S_DMA_CHAN_PRIORITY, \
.channel_priority = STM32_DMA_CONFIG_PRIORITY( \
DT_I2S_##index##_DMA_CHANNEL_CONFIG_##dir_cap), \
.dma_callback = dma_##dir##_callback, \
}, \
.src_addr_increment = I2S_DMA_SRC_ADDR_INC_##dir_cap, \
.dst_addr_increment = I2S_DMA_DST_ADDR_INC_##dir_cap, \
.fifo_threshold = I2S_DMA_FIFO_THRESHOLD, \
.src_addr_increment = STM32_DMA_CONFIG_##src_dev##_ADDR_INC( \
DT_I2S_##index##_DMA_CHANNEL_CONFIG_##dir_cap), \
.dst_addr_increment = STM32_DMA_CONFIG_##dest_dev##_ADDR_INC( \
DT_I2S_##index##_DMA_CHANNEL_CONFIG_##dir_cap), \
.fifo_threshold = STM32_DMA_FEATURES_FIFO_THRESHOLD( \
DT_I2S_##index##_DMA_FEATURES_##dir_cap), \
.stream_start = dir##_stream_start, \
.stream_disable = dir##_stream_disable, \
.queue_drop = dir##_queue_drop, \
@ -881,9 +888,8 @@ struct queue_item rx_##index##_ring_buf[CONFIG_I2S_STM32_RX_BLOCK_COUNT + 1];\
struct queue_item tx_##index##_ring_buf[CONFIG_I2S_STM32_TX_BLOCK_COUNT + 1];\
\
static struct i2s_stm32_data i2s_stm32_data_##index = { \
.dma_name = I2S##index##_DMA_CHAN_RX, \
I2S_DMA_CHANNEL_INIT(index, rx, RX), \
I2S_DMA_CHANNEL_INIT(index, tx, TX), \
I2S_DMA_CHANNEL_INIT(index, rx, RX, PERIPH, MEM), \
I2S_DMA_CHANNEL_INIT(index, tx, TX, MEM, PERIPH), \
}; \
DEVICE_AND_API_INIT(i2s_stm32_##index, DT_I2S_##index##_NAME, \
&i2s_stm32_initialize, &i2s_stm32_data_##index, \

View file

@ -49,40 +49,6 @@
#endif /* CONFIG_I2S_STM32_USE_PLLI2S_ENABLE */
#ifdef CONFIG_SOC_SERIES_STM32F4X
#define I2S1_DMA_NAME CONFIG_DMA_2_NAME
#define I2S1_DMA_CHAN_RX 2
#define I2S1_DMA_SLOT_RX 3
#define I2S1_DMA_CHAN_TX 3
#define I2S1_DMA_SLOT_TX 3
#define I2S2_DMA_NAME CONFIG_DMA_1_NAME
#define I2S2_DMA_CHAN_RX 3
#define I2S2_DMA_SLOT_RX 0
#define I2S2_DMA_CHAN_TX 4
#define I2S2_DMA_SLOT_TX 0
#define I2S3_DMA_NAME CONFIG_DMA_1_NAME
#define I2S3_DMA_CHAN_RX 0
#define I2S3_DMA_SLOT_RX 0
#define I2S3_DMA_CHAN_TX 5
#define I2S3_DMA_SLOT_TX 0
#define I2S4_DMA_NAME CONFIG_DMA_2_NAME
#define I2S4_DMA_CHAN_RX 0
#define I2S4_DMA_SLOT_RX 4
#define I2S4_DMA_CHAN_TX 1
#define I2S4_DMA_SLOT_TX 4
#define I2S5_DMA_NAME CONFIG_DMA_2_NAME
#define I2S5_DMA_CHAN_RX 5
#define I2S5_DMA_SLOT_RX 7
#define I2S5_DMA_CHAN_TX 6
#define I2S5_DMA_SLOT_TX 7
#define I2S_DMA_SRC_ADDR_INC_RX 0
#define I2S_DMA_DST_ADDR_INC_RX 1
#define I2S_DMA_SRC_ADDR_INC_TX 1
#define I2S_DMA_DST_ADDR_INC_TX 0
#define I2S_DMA_FIFO_THRESHOLD 3 /* Full FIFO */
#define I2S_DMA_CHAN_PRIORITY 0
#endif
#define DEV_CFG(dev) \
(const struct i2s_stm32_cfg * const)((dev)->config->config_info)
#define DEV_DATA(dev) \
@ -112,6 +78,8 @@ struct i2s_stm32_cfg {
struct stream {
s32_t state;
struct k_sem sem;
const char *dma_name;
u32_t dma_channel;
struct dma_config dma_cfg;
u8_t priority;

View file

@ -213,6 +213,9 @@
reg = <0x40013000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
interrupts = <35 5>;
dmas = <&dma2 3 3 0x400 0x3
&dma2 2 3 0x400 0x3>;
dma-names = "tx", "rx";
status = "disabled";
label = "I2S_1";
};

View file

@ -37,6 +37,9 @@
reg = <0x40003800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
interrupts = <36 5>;
dmas = <&dma1 4 0 0x400 0x3
&dma1 3 0 0x400 0x3>;
dma-names = "tx", "rx";
status = "disabled";
label = "I2S_2";
};
@ -48,6 +51,9 @@
reg = <0x40003c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
interrupts = <51 5>;
dmas = <&dma1 5 0 0x400 0x3
&dma1 0 0 0x400 0x3>;
dma-names = "tx", "rx";
status = "disabled";
label = "I2S_3";
};

View file

@ -35,6 +35,9 @@
reg = <0x40013400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
interrupts = <84 5>;
dmas = <&dma2 1 4 0x400 0x3
&dma2 0 4 0x400 0x3>;
dma-names = "tx", "rx";
status = "disabled";
label = "I2S_4";
};
@ -46,6 +49,9 @@
reg = <0x40015000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
interrupts = <85 5>;
dmas = <&dma2 6 7 0x400 0x3
&dma2 5 7 0x400 0x3>;
dma-names = "tx", "rx";
status = "disabled";
label = "I2S_5";
};

16
dts/bindings/dma/dma.yaml Normal file
View file

@ -0,0 +1,16 @@
# Copyright (c) 2019, Linaro Limited
# Copyright (c) 2019, Song Qiang <songqiang1304521@gmail.com>
# SPDX-License-Identifier: Apache-2.0
# Common fields for DMA users
properties:
dmas:
required: true
type: phandle-array
description: DMA instances information
dma-names:
required: false
type: string-array
description: name of each dma instance

View file

@ -8,7 +8,7 @@ description: |
compatible: "st,stm32-i2s"
include: i2s-controller.yaml
include: [i2s-controller.yaml, dma.yaml]
properties:
reg:
@ -16,3 +16,6 @@ properties:
interrupts:
required: true
dma-names:
required: true

View file

@ -244,6 +244,22 @@
#define DT_I2S_1_IRQ DT_ST_STM32_I2S_40013000_IRQ_0
#define DT_I2S_1_CLOCK_BITS DT_ST_STM32_I2S_40013000_CLOCK_BITS
#define DT_I2S_1_CLOCK_BUS DT_ST_STM32_I2S_40013000_CLOCK_BUS
#define DT_I2S_1_DMA_CONTROLLER_TX \
DT_ST_STM32_I2S_40013000_TX_DMAS_CONTROLLER
#define DT_I2S_1_DMA_CHANNEL_TX DT_ST_STM32_I2S_40013000_TX_DMAS_CHANNEL
#define DT_I2S_1_DMA_SLOT_TX DT_ST_STM32_I2S_40013000_TX_DMAS_SLOT
#define DT_I2S_1_DMA_CHANNEL_CONFIG_TX \
DT_ST_STM32_I2S_40013000_TX_DMAS_CHANNEL_CONFIG
#define DT_I2S_1_DMA_FEATURES_TX \
DT_ST_STM32_I2S_40013000_TX_DMAS_FEATURES
#define DT_I2S_1_DMA_CONTROLLER_RX \
DT_ST_STM32_I2S_40013000_RX_DMAS_CONTROLLER
#define DT_I2S_1_DMA_CHANNEL_RX DT_ST_STM32_I2S_40013000_RX_DMAS_CHANNEL
#define DT_I2S_1_DMA_SLOT_RX DT_ST_STM32_I2S_40013000_RX_DMAS_SLOT
#define DT_I2S_1_DMA_CHANNEL_CONFIG_RX \
DT_ST_STM32_I2S_40013000_RX_DMAS_CHANNEL_CONFIG
#define DT_I2S_1_DMA_FEATURES_RX \
DT_ST_STM32_I2S_40013000_RX_DMAS_FEATURES
#define DT_I2S_2_BASE_ADDRESS DT_ST_STM32_I2S_40003800_BASE_ADDRESS
#define DT_I2S_2_IRQ_PRI DT_ST_STM32_I2S_40003800_IRQ_0_PRIORITY
@ -251,6 +267,22 @@
#define DT_I2S_2_IRQ DT_ST_STM32_I2S_40003800_IRQ_0
#define DT_I2S_2_CLOCK_BITS DT_ST_STM32_I2S_40003800_CLOCK_BITS
#define DT_I2S_2_CLOCK_BUS DT_ST_STM32_I2S_40003800_CLOCK_BUS
#define DT_I2S_2_DMA_CONTROLLER_TX \
DT_ST_STM32_I2S_40003800_TX_DMAS_CONTROLLER
#define DT_I2S_2_DMA_CHANNEL_TX DT_ST_STM32_I2S_40003800_TX_DMAS_CHANNEL
#define DT_I2S_2_DMA_SLOT_TX DT_ST_STM32_I2S_40003800_TX_DMAS_SLOT
#define DT_I2S_2_DMA_CHANNEL_CONFIG_TX \
DT_ST_STM32_I2S_40003800_TX_DMAS_CHANNEL_CONFIG
#define DT_I2S_2_DMA_FEATURES_TX \
DT_ST_STM32_I2S_40003800_TX_DMAS_FEATURES
#define DT_I2S_2_DMA_CONTROLLER_RX \
DT_ST_STM32_I2S_40003800_RX_DMAS_CONTROLLER
#define DT_I2S_2_DMA_CHANNEL_RX DT_ST_STM32_I2S_40003800_RX_DMAS_CHANNEL
#define DT_I2S_2_DMA_SLOT_RX DT_ST_STM32_I2S_40003800_RX_DMAS_SLOT
#define DT_I2S_2_DMA_CHANNEL_CONFIG_RX \
DT_ST_STM32_I2S_40003800_RX_DMAS_CHANNEL_CONFIG
#define DT_I2S_2_DMA_FEATURES_RX \
DT_ST_STM32_I2S_40003800_RX_DMAS_FEATURES
#define DT_I2S_3_BASE_ADDRESS DT_ST_STM32_I2S_40003C00_BASE_ADDRESS
#define DT_I2S_3_IRQ_PRI DT_ST_STM32_I2S_40003C00_IRQ_0_PRIORITY
@ -258,6 +290,22 @@
#define DT_I2S_3_IRQ DT_ST_STM32_I2S_40003C00_IRQ_0
#define DT_I2S_3_CLOCK_BITS DT_ST_STM32_I2S_40003C00_CLOCK_BITS
#define DT_I2S_3_CLOCK_BUS DT_ST_STM32_I2S_40003C00_CLOCK_BUS
#define DT_I2S_3_DMA_CONTROLLER_TX \
DT_ST_STM32_I2S_40003C00_TX_DMAS_CONTROLLER
#define DT_I2S_3_DMA_CHANNEL_TX DT_ST_STM32_I2S_40003C00_TX_DMAS_CHANNEL
#define DT_I2S_3_DMA_SLOT_TX DT_ST_STM32_I2S_40003C00_TX_DMAS_SLOT
#define DT_I2S_3_DMA_CHANNEL_CONFIG_TX \
DT_ST_STM32_I2S_40003C00_TX_DMAS_CHANNEL_CONFIG
#define DT_I2S_3_DMA_FEATURES_TX \
DT_ST_STM32_I2S_40003C00_TX_DMAS_FEATURES
#define DT_I2S_3_DMA_CONTROLLER_RX \
DT_ST_STM32_I2S_40003C00_RX_DMAS_CONTROLLER
#define DT_I2S_3_DMA_CHANNEL_RX DT_ST_STM32_I2S_40003C00_RX_DMAS_CHANNEL
#define DT_I2S_3_DMA_SLOT_RX DT_ST_STM32_I2S_40003C00_RX_DMAS_SLOT
#define DT_I2S_3_DMA_CHANNEL_CONFIG_RX \
DT_ST_STM32_I2S_40003C00_RX_DMAS_CHANNEL_CONFIG
#define DT_I2S_3_DMA_FEATURES_RX \
DT_ST_STM32_I2S_40003C00_RX_DMAS_FEATURES
#define DT_I2S_4_BASE_ADDRESS DT_ST_STM32_I2S_40013400_BASE_ADDRESS
#define DT_I2S_4_IRQ_PRI DT_ST_STM32_I2S_40013400_IRQ_0_PRIORITY
@ -265,6 +313,22 @@
#define DT_I2S_4_IRQ DT_ST_STM32_I2S_40013400_IRQ_0
#define DT_I2S_4_CLOCK_BITS DT_ST_STM32_I2S_40013400_CLOCK_BITS
#define DT_I2S_4_CLOCK_BUS DT_ST_STM32_I2S_40013400_CLOCK_BUS
#define DT_I2S_4_DMA_CONTROLLER_TX \
DT_ST_STM32_I2S_40013400_TX_DMAS_CONTROLLER
#define DT_I2S_4_DMA_CHANNEL_TX DT_ST_STM32_I2S_40013400_TX_DMAS_CHANNEL
#define DT_I2S_4_DMA_SLOT_TX DT_ST_STM32_I2S_40013400_TX_DMAS_SLOT
#define DT_I2S_4_DMA_CHANNEL_CONFIG_TX \
DT_ST_STM32_I2S_40013400_TX_DMAS_CHANNEL_CONFIG
#define DT_I2S_4_DMA_FEATURES_TX \
DT_ST_STM32_I2S_40013400_TX_DMAS_FEATURES
#define DT_I2S_4_DMA_CONTROLLER_RX \
DT_ST_STM32_I2S_40013400_RX_DMAS_CONTROLLER
#define DT_I2S_4_DMA_CHANNEL_RX DT_ST_STM32_I2S_40013400_RX_DMAS_CHANNEL
#define DT_I2S_4_DMA_SLOT_RX DT_ST_STM32_I2S_40013400_RX_DMAS_SLOT
#define DT_I2S_4_DMA_CHANNEL_CONFIG_RX \
DT_ST_STM32_I2S_40013400_RX_DMAS_CHANNEL_CONFIG
#define DT_I2S_4_DMA_FEATURES_RX \
DT_ST_STM32_I2S_40013400_RX_DMAS_FEATURES
#define DT_I2S_5_BASE_ADDRESS DT_ST_STM32_I2S_40015000_BASE_ADDRESS
#define DT_I2S_5_IRQ_PRI DT_ST_STM32_I2S_40015000_IRQ_0_PRIORITY
@ -272,6 +336,22 @@
#define DT_I2S_5_IRQ DT_ST_STM32_I2S_40015000_IRQ_0
#define DT_I2S_5_CLOCK_BITS DT_ST_STM32_I2S_40015000_CLOCK_BITS
#define DT_I2S_5_CLOCK_BUS DT_ST_STM32_I2S_40015000_CLOCK_BUS
#define DT_I2S_5_DMA_CONTROLLER_TX \
DT_ST_STM32_I2S_40015000_TX_DMAS_CONTROLLER
#define DT_I2S_5_DMA_CHANNEL_TX DT_ST_STM32_I2S_40015000_TX_DMAS_CHANNEL
#define DT_I2S_5_DMA_SLOT_TX DT_ST_STM32_I2S_40015000_TX_DMAS_SLOT
#define DT_I2S_5_DMA_CHANNEL_CONFIG_TX \
DT_ST_STM32_I2S_40015000_TX_DMAS_CHANNEL_CONFIG
#define DT_I2S_5_DMA_FEATURES_TX \
DT_ST_STM32_I2S_40015000_TX_DMAS_FEATURES
#define DT_I2S_5_DMA_CONTROLLER_RX \
DT_ST_STM32_I2S_40015000_RX_DMAS_CONTROLLER
#define DT_I2S_5_DMA_CHANNEL_RX DT_ST_STM32_I2S_40015000_RX_DMAS_CHANNEL
#define DT_I2S_5_DMA_SLOT_RX DT_ST_STM32_I2S_40015000_RX_DMAS_SLOT
#define DT_I2S_5_DMA_CHANNEL_CONFIG_RX \
DT_ST_STM32_I2S_40015000_RX_DMAS_CHANNEL_CONFIG
#define DT_I2S_5_DMA_FEATURES_RX \
DT_ST_STM32_I2S_40015000_RX_DMAS_FEATURES
#define DT_I2S_6_BASE_ADDRESS DT_ST_STM32_I2S_40015400_BASE_ADDRESS
#define DT_I2S_6_IRQ_PRI DT_ST_STM32_I2S_40015400_IRQ_0_PRIORITY
@ -279,6 +359,22 @@
#define DT_I2S_6_IRQ DT_ST_STM32_I2S_40015400_IRQ_0
#define DT_I2S_6_CLOCK_BITS DT_ST_STM32_I2S_40015400_CLOCK_BITS
#define DT_I2S_6_CLOCK_BUS DT_ST_STM32_I2S_40015400_CLOCK_BUS
#define DT_I2S_6_DMA_CONTROLLER_TX \
DT_ST_STM32_I2S_40015400_TX_DMAS_CONTROLLER
#define DT_I2S_6_DMA_CHANNEL_TX DT_ST_STM32_I2S_40015400_TX_DMAS_CHANNEL
#define DT_I2S_6_DMA_SLOT_TX DT_ST_STM32_I2S_40015400_TX_DMAS_SLOT
#define DT_I2S_6_DMA_CHANNEL_CONFIG_TX \
DT_ST_STM32_I2S_40015400_TX_DMAS_CHANNEL_CONFIG
#define DT_I2S_6_DMA_FEATURES_TX \
DT_ST_STM32_I2S_40015400_TX_DMAS_FEATURES
#define DT_I2S_6_DMA_CONTROLLER_RX \
DT_ST_STM32_I2S_40015400_RX_DMAS_CONTROLLER
#define DT_I2S_6_DMA_CHANNEL_RX DT_ST_STM32_I2S_40015400_RX_DMAS_CHANNEL
#define DT_I2S_6_DMA_SLOT_RX DT_ST_STM32_I2S_40015400_RX_DMAS_SLOT
#define DT_I2S_6_DMA_CHANNEL_CONFIG_RX \
DT_ST_STM32_I2S_40015400_RX_DMAS_CHANNEL_CONFIG
#define DT_I2S_6_DMA_FEATURES_RX \
DT_ST_STM32_I2S_40015400_RX_DMAS_FEATURES
#define DT_FLASH_DEV_BASE_ADDRESS DT_ST_STM32F4_FLASH_CONTROLLER_40023C00_BASE_ADDRESS
#define DT_FLASH_DEV_NAME DT_ST_STM32F4_FLASH_CONTROLLER_40023C00_LABEL