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soc: arm: st_stm32: add STM32F437XI

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This patch adds support for the STM32F437XI SoC.

Signed-off-by: Markus Fuchs <markus.fuchs@de.sauter-bc.com>
This commit is contained in:
Markus Fuchs 2019-07-09 22:23:39 +02:00 • committed by Kumar Gala
commit edb58ec46b
5 changed files with 172 additions and 0 deletions
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87
dts/arm/st/f4/stm32f437.dtsi Normal file
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@ -0,0 +1,87 @@
/*
* Copyright (c) 2019, Markus Fuchs <markus.fuchs@de.sauter-bc.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f4/stm32f407.dtsi>
/ {
soc {
pinctrl: pin-controller@40020000 {
reg = <0x40020000 0x2C00>;
gpioj: gpio@40022400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40022400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000200>;
label = "GPIOJ";
};
gpiok: gpio@40022800 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40022800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000400>;
label = "GPIOK";
};
};
uart7: serial@40007800 {
compatible = "st,stm32-uart";
reg = <0x40007800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
interrupts = <82 0>;
status = "disabled";
label = "UART_7";
};
uart8: serial@40007c00 {
compatible = "st,stm32-uart";
reg = <0x40007c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
interrupts = <83 0>;
status = "disabled";
label = "UART_8";
};
spi4: spi@40013400 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013400 0x400>;
interrupts = <84 5>;
status = "disabled";
label = "SPI_4";
};
/* spi5 is present on all STM32F437XX SoCs except
* STM32F437vX SoCs. Delete node in stm32f437vX.dtsi.
*/
spi5: spi@40015000 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40015000 0x400>;
interrupts = <85 5>;
status = "disabled";
label = "SPI_5";
};
/* spi6 is present on all STM32F437XX SoCs except
* STM32F437vX SoCs. Delete node in stm32f437vX.dtsi.
*/
spi6: spi@40015400 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40015400 0x400>;
interrupts = <86 5>;
status = "disabled";
label = "SPI_6";
};
};
};

27
dts/arm/st/f4/stm32f437Xi.dtsi Normal file
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/*
* Copyright (c) 2019, Markus Fuchs <markus.fuchs@de.sauter-bc.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f4/stm32f437.dtsi>
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(64)>;
};
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(192)>;
};
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(2048)>;
};
};
};
};

11
dts/arm/st/f4/stm32f437vX.dtsi Normal file
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@ -0,0 +1,11 @@
/*
* Copyright (c) 2019, Markus Fuchs <markus.fuchs@de.sauter-bc.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f4/stm32f437.dtsi>
/delete-node/ &spi5;
/delete-node/ &spi6;

44
soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f437xx Normal file
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@ -0,0 +1,44 @@
# Kconfig - ST STM32F437XX MCU configuration options
#
# Copyright (c) 2019, Markus Fuchs <markus.fuchs@de.sauter-bc.com>
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_STM32F437XX
config SOC
string
default "stm32f437xx"
config NUM_IRQS
int
default 91
if GPIO_STM32
config GPIO_STM32_PORTF
default y
config GPIO_STM32_PORTG
default y
config GPIO_STM32_PORTI
default y
config GPIO_STM32_PORTJ
default y
config GPIO_STM32_PORTK
default y
endif # GPIO_STM32
if ENTROPY_GENERATOR
config ENTROPY_STM32_RNG
default y
endif # ENTROPY_GENERATOR
endif # SOC_STM32F437XX

3
soc/arm/st_stm32/stm32f4/Kconfig.soc
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@ -39,6 +39,9 @@ config SOC_STM32F417XX
config SOC_STM32F429XX
bool "STM32F429XI"
config SOC_STM32F437XX
bool "STM32F437XX"
config SOC_STM32F446XX
bool "STM32F446XX"