soc: arm: st_stm32: add STM32F437XI
This patch adds support for the STM32F437XI SoC. Signed-off-by: Markus Fuchs <markus.fuchs@de.sauter-bc.com>
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87
dts/arm/st/f4/stm32f437.dtsi
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87
dts/arm/st/f4/stm32f437.dtsi
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/*
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* Copyright (c) 2019, Markus Fuchs <markus.fuchs@de.sauter-bc.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/f4/stm32f407.dtsi>
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/ {
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soc {
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pinctrl: pin-controller@40020000 {
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reg = <0x40020000 0x2C00>;
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gpioj: gpio@40022400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40022400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000200>;
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label = "GPIOJ";
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};
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gpiok: gpio@40022800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x40022800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000400>;
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label = "GPIOK";
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};
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};
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uart7: serial@40007800 {
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compatible = "st,stm32-uart";
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reg = <0x40007800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
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interrupts = <82 0>;
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status = "disabled";
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label = "UART_7";
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};
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uart8: serial@40007c00 {
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compatible = "st,stm32-uart";
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reg = <0x40007c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
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interrupts = <83 0>;
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status = "disabled";
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label = "UART_8";
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};
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spi4: spi@40013400 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013400 0x400>;
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interrupts = <84 5>;
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status = "disabled";
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label = "SPI_4";
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};
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/* spi5 is present on all STM32F437XX SoCs except
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* STM32F437vX SoCs. Delete node in stm32f437vX.dtsi.
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*/
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spi5: spi@40015000 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40015000 0x400>;
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interrupts = <85 5>;
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status = "disabled";
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label = "SPI_5";
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};
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/* spi6 is present on all STM32F437XX SoCs except
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* STM32F437vX SoCs. Delete node in stm32f437vX.dtsi.
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*/
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spi6: spi@40015400 {
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compatible = "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40015400 0x400>;
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interrupts = <86 5>;
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status = "disabled";
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label = "SPI_6";
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};
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};
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};
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27
dts/arm/st/f4/stm32f437Xi.dtsi
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27
dts/arm/st/f4/stm32f437Xi.dtsi
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/*
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* Copyright (c) 2019, Markus Fuchs <markus.fuchs@de.sauter-bc.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <st/f4/stm32f437.dtsi>
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/ {
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ccm0: memory@10000000 {
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compatible = "st,stm32-ccm";
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reg = <0x10000000 DT_SIZE_K(64)>;
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};
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(192)>;
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};
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soc {
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flash-controller@40023c00 {
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flash0: flash@8000000 {
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reg = <0x08000000 DT_SIZE_K(2048)>;
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};
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};
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};
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};
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11
dts/arm/st/f4/stm32f437vX.dtsi
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11
dts/arm/st/f4/stm32f437vX.dtsi
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/*
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* Copyright (c) 2019, Markus Fuchs <markus.fuchs@de.sauter-bc.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/f4/stm32f437.dtsi>
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/delete-node/ &spi5;
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/delete-node/ &spi6;
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44
soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f437xx
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44
soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f437xx
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# Kconfig - ST STM32F437XX MCU configuration options
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#
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# Copyright (c) 2019, Markus Fuchs <markus.fuchs@de.sauter-bc.com>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_STM32F437XX
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config SOC
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string
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default "stm32f437xx"
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config NUM_IRQS
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int
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default 91
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if GPIO_STM32
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config GPIO_STM32_PORTF
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default y
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config GPIO_STM32_PORTG
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default y
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config GPIO_STM32_PORTI
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default y
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config GPIO_STM32_PORTJ
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default y
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config GPIO_STM32_PORTK
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default y
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endif # GPIO_STM32
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if ENTROPY_GENERATOR
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config ENTROPY_STM32_RNG
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default y
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endif # ENTROPY_GENERATOR
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endif # SOC_STM32F437XX
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@ -39,6 +39,9 @@ config SOC_STM32F417XX
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config SOC_STM32F429XX
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bool "STM32F429XI"
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config SOC_STM32F437XX
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bool "STM32F437XX"
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config SOC_STM32F446XX
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bool "STM32F446XX"
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