drivers: timer: add RTC support as system clock for CC13X2/CC26X2
Add RTC timer driver for CC13X2/CC26X2, and use it instead of systick as system clock. It is necessary to use this timer for power management support, so that the system can exit from deep sleep upon expiry of timeouts. Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
This commit is contained in:
Vincent Wan
Kumar Gala
parent
cf7555a841
commit
aeb8d017b5
10 changed files with 297 additions and 3 deletions
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@ -82,3 +82,7 @@
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cs-pin = <11>;
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cs-gpios = <&gpio0 11 0>;
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};
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&rtc {
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status = "okay";
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};
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@ -7,7 +7,6 @@
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CONFIG_ARM=y
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CONFIG_SOC_SERIES_CC13X2_CC26X2=y
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CONFIG_SOC_CC1352R=y
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CONFIG_CORTEX_M_SYSTICK=y
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CONFIG_BOARD_CC1352R1_LAUNCHXL=y
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CONFIG_CC13X2_CC26X2_BOOTLOADER_ENABLE=y
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@ -82,3 +82,7 @@
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cs-pin = <11>;
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cs-gpios = <&gpio0 11 0>;
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};
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&rtc {
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status = "okay";
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};
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@ -7,7 +7,6 @@
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CONFIG_ARM=y
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CONFIG_SOC_SERIES_CC13X2_CC26X2=y
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CONFIG_SOC_CC2652R=y
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CONFIG_CORTEX_M_SYSTICK=y
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CONFIG_BOARD_CC26X2R1_LAUNCHXL=y
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CONFIG_CC13X2_CC26X2_BOOTLOADER_ENABLE=y
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@ -16,3 +16,4 @@ zephyr_sources_if_kconfig( sam0_rtc_timer.c)
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zephyr_sources_if_kconfig( litex_timer.c)
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zephyr_sources_if_kconfig( mchp_xec_rtos_timer.c)
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zephyr_sources_if_kconfig( xlnx_psttc_timer.c)
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zephyr_sources_if_kconfig( cc13x2_cc26x2_rtc_timer.c)
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@ -220,6 +220,15 @@ config MCHP_XEC_RTOS_TIMER
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XEC series RTOS timer and provides the standard "system clock
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driver" interfaces.
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config CC13X2_CC26X2_RTC_TIMER
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bool "TI SimpleLink CC13x2/CC26x2 RTC timer"
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depends on SOC_SERIES_CC13X2_CC26X2
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select TICKLESS_CAPABLE
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help
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This module implements a kernel device driver for the TI SimpleLink
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CC13X2_CC26X2 series Real Time Counter and provides the standard
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"system clock driver" interfaces.
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config XLNX_PSTTC_TIMER
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bool "Xilinx PS ttc timer support"
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default y
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242
drivers/timer/cc13x2_cc26x2_rtc_timer.c
Normal file
242
drivers/timer/cc13x2_cc26x2_rtc_timer.c
Normal file
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@ -0,0 +1,242 @@
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/*
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* Copyright (c) 2019, Texas Instruments Incorporated
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* TI SimpleLink CC13X2/CC26X2 RTC-based system timer
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*
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* This system timer implementation supports both tickless and ticking modes.
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* RTC counts continually in 64-bit mode and timeouts are
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* scheduled using the RTC comparator. An interrupt is triggered whenever
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* the comparator value set is reached.
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*/
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#include <soc.h>
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#include <drivers/clock_control.h>
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#include <drivers/timer/system_timer.h>
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#include <sys_clock.h>
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#include <driverlib/interrupt.h>
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#include <driverlib/aon_rtc.h>
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#include <driverlib/aon_event.h>
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#define RTC_COUNTS_PER_SEC 0x100000000ULL
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/* Number of counts per rtc timer cycle */
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#define RTC_COUNTS_PER_CYCLE (RTC_COUNTS_PER_SEC / \
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sys_clock_hw_cycles_per_sec())
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/* Number of counts per system clock tick */
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#define RTC_COUNTS_PER_TICK (RTC_COUNTS_PER_SEC / \
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CONFIG_SYS_CLOCK_TICKS_PER_SEC)
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/* Number of RTC cycles per system clock tick */
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#define CYCLES_PER_TICK (sys_clock_hw_cycles_per_sec() / \
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CONFIG_SYS_CLOCK_TICKS_PER_SEC)
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/*
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* Maximum number of ticks.
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*/
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#define MAX_TICKS (0x7FFFFFFFFFFFULL / RTC_COUNTS_PER_TICK)
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/*
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* Due to the nature of clock synchronization, the comparator cannot be set
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* to a value that is too close to the current time. This constant defines
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* a safe threshold for the comparator.
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*/
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#define COMPARE_MARGIN 6
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/* RTC count of the last announce call, rounded down to tick boundary. */
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static volatile u64_t rtc_last;
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#ifdef CONFIG_TICKLESS_KERNEL
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static struct k_spinlock lock;
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#else
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static u64_t nextThreshold = RTC_COUNTS_PER_TICK;
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#endif /* CONFIG_TICKLESS_KERNEL */
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static void setThreshold(u32_t next)
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{
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u32_t now;
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unsigned int key;
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key = irq_lock();
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/* get the current RTC count corresponding to compare window */
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now = AONRTCCurrentCompareValueGet();
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/* if next is too soon, set at least one RTC tick in future */
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/* assume next never be more than half the maximum 32 bit count value */
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if ((next - now) > (u32_t)0x80000000) {
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/* now is past next */
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next = now + COMPARE_MARGIN;
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} else if ((now + COMPARE_MARGIN - next) < (u32_t)0x80000000) {
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if (next < now + COMPARE_MARGIN) {
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next = now + COMPARE_MARGIN;
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}
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}
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/* set next compare threshold in RTC */
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AONRTCCompareValueSet(AON_RTC_CH0, next);
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irq_unlock(key);
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}
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void rtc_isr(void *arg)
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{
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#ifndef CONFIG_TICKLESS_KERNEL
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u64_t newThreshold;
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u32_t next;
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#else
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u64_t ticks, currCount;
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#endif
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ARG_UNUSED(arg);
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AONRTCEventClear(AON_RTC_CH0);
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#ifdef CONFIG_TICKLESS_KERNEL
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k_spinlock_key_t key = k_spin_lock(&lock);
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currCount = (u64_t)AONRTCCurrent64BitValueGet();
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ticks = (currCount - rtc_last) / RTC_COUNTS_PER_TICK;
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rtc_last += ticks * RTC_COUNTS_PER_TICK;
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k_spin_unlock(&lock, key);
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z_clock_announce(ticks);
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#else /* !CONFIG_TICKLESS_KERNEL */
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/* calculate new 64-bit RTC count for next interrupt */
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newThreshold = nextThreshold + RTC_COUNTS_PER_TICK;
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next = (u32_t)((u64_t)newThreshold >> 16);
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setThreshold(next);
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nextThreshold = newThreshold;
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rtc_last += RTC_COUNTS_PER_TICK;
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z_clock_announce(1);
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#endif /* CONFIG_TICKLESS_KERNEL */
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}
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static void initDevice(void)
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{
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AONRTCDisable();
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AONRTCReset();
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HWREG(AON_RTC_BASE + AON_RTC_O_SYNC) = 1;
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/* read sync register to complete reset */
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HWREG(AON_RTC_BASE + AON_RTC_O_SYNC);
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AONRTCEventClear(AON_RTC_CH0);
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IntPendClear(INT_AON_RTC_COMB);
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HWREG(AON_RTC_BASE + AON_RTC_O_SYNC);
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}
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static void startDevice(void)
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{
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u32_t compare;
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u64_t period;
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unsigned int key;
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key = irq_lock();
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/* reset timer */
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AONRTCReset();
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AONRTCEventClear(AON_RTC_CH0);
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IntPendClear(INT_AON_RTC_COMB);
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/*
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* set the compare register to one period.
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* For a very small period round up to interrupt upon 4th tick in
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* compare register
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*/
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period = RTC_COUNTS_PER_TICK;
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if (period < 0x40000) {
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compare = 0x4; /* 4 * 15.5us ~= 62us */
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} else {
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/* else, interrupt on first period expiration */
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compare = period >> 16;
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}
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/* set the compare value at the RTC */
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AONRTCCompareValueSet(AON_RTC_CH0, compare);
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/* enable compare channel 0 */
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AONEventMcuWakeUpSet(AON_EVENT_MCU_WU0, AON_EVENT_RTC0);
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AONRTCChannelEnable(AON_RTC_CH0);
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AONRTCCombinedEventConfig(AON_RTC_CH0);
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/* start timer */
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AONRTCEnable();
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irq_unlock(key);
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}
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int z_clock_driver_init(struct device *device)
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{
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ARG_UNUSED(device);
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rtc_last = 0U;
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initDevice();
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startDevice();
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/* Enable RTC interrupt. */
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IRQ_CONNECT(DT_INST_0_TI_CC13XX_CC26XX_RTC_IRQ_0,
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DT_INST_0_TI_CC13XX_CC26XX_RTC_IRQ_0_PRIORITY,
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rtc_isr, 0, 0);
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irq_enable(DT_INST_0_TI_CC13XX_CC26XX_RTC_IRQ_0);
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return 0;
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}
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void z_clock_set_timeout(s32_t ticks, bool idle)
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{
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ARG_UNUSED(idle);
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#ifdef CONFIG_TICKLESS_KERNEL
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ticks = (ticks == K_FOREVER) ? MAX_TICKS : ticks;
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ticks = MAX(MIN(ticks - 1, (s32_t) MAX_TICKS), 0);
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k_spinlock_key_t key = k_spin_lock(&lock);
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/* Compute number of RTC cycles until the next timeout. */
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u64_t count = AONRTCCurrent64BitValueGet();
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u64_t timeout = ticks * RTC_COUNTS_PER_TICK +
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(count - rtc_last);
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/* Round to the nearest tick boundary. */
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timeout = (timeout + RTC_COUNTS_PER_TICK - 1) / RTC_COUNTS_PER_TICK
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* RTC_COUNTS_PER_TICK;
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timeout += rtc_last;
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/* Set the comparator */
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setThreshold(timeout >> 16);
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k_spin_unlock(&lock, key);
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#endif /* CONFIG_TICKLESS_KERNEL */
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}
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u32_t z_clock_elapsed(void)
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{
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u32_t ret = (AONRTCCurrent64BitValueGet() - rtc_last) /
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RTC_COUNTS_PER_TICK;
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return ret;
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}
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u32_t z_timer_cycle_get_32(void)
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{
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return (AONRTCCurrent64BitValueGet() / RTC_COUNTS_PER_CYCLE)
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& 0xFFFFFFFF;
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}
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@ -113,6 +113,14 @@
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status = "disabled";
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label = "SPI_1";
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};
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rtc: rtc@40092000 {
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compatible = "ti,cc13xx-cc26xx-rtc";
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reg = <0x40092000 0x1000>;
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interrupts = <4 0>; /* interrupt #20 = 4 + 16 */
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status = "disabled";
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label = "RTC";
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};
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};
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};
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18
dts/bindings/rtc/ti,cc13xx-cc26xx-rtc.yaml
Normal file
18
dts/bindings/rtc/ti,cc13xx-cc26xx-rtc.yaml
Normal file
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@ -0,0 +1,18 @@
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#
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# Copyright (c) 2019, Texas Instruments Incorporated
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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title: TI SimpleLink CC13xx/CC26xx RTC
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description: >
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This binding gives a base representation of the TI SimpleLink CC13xx/CC26xx RTC
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compatible: "ti,cc13xx-cc26xx-rtc"
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include: rtc.yaml
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properties:
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reg:
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required: true
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@ -15,7 +15,14 @@ config SOC_SERIES
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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int
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default 48000000
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default 32768
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# Note that when using the RTC as system clock, this needs to be 32768
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# to reduce truncation errors from accumulating due to conversion to/from
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# time, ticks, and HW cycles
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config SYS_CLOCK_TICKS_PER_SEC
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int
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default 32768
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config NUM_IRQS
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int
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@ -25,6 +32,9 @@ config TI_CCFG_PRESENT
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bool
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default y
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config CC13X2_CC26X2_RTC_TIMER
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default y
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if PINMUX
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config PINMUX_CC13XX_CC26XX
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