arch: arm: nrf: Add support for the nRF52810
The nRF52810 is a low-cost variant of the nRF52832, with a reduced set of peripherals and memory. This commit adds basic support for it in the arch SoC and dts folders. Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no> Signed-off-by: Ioannis Glaropoulos <ioannis.glaropoulos@nordicsemi.no>
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10 changed files with 154 additions and 4 deletions
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@ -1,3 +1,4 @@
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zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF52810 NRF52810_XXAA)
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zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF52832 NRF52832_XXAA)
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zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF52840 NRF52840_XXAA)
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@ -0,0 +1,20 @@
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# Kconfig.defconfig.nrf52810 - Nordic Semiconductor nRF52810 MCU
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#
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# Copyright (c) 2018 Nordic Semiconductor ASA
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_NRF52810_QFAA
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config SOC
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string
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default "nRF52810_QFAA"
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config NUM_IRQS
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int
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default 30
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endif # SOC_NRF52810_QFAA
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@ -180,6 +180,11 @@ choice
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prompt "nRF52x MCU Selection"
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depends on SOC_SERIES_NRF52X
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config SOC_NRF52810_QFAA
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bool "NRF52810_QFAA"
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select SOC_NRF52810
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select HAS_SEGGER_RTT
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config SOC_NRF52832_QFAA
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bool "NRF52832_QFAA"
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select SOC_NRF52832
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@ -207,7 +212,7 @@ config ARM_MPU_NRF52X
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config NFCT_PINS_AS_GPIOS
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bool "NFCT pins as GPIOs"
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depends on SOC_SERIES_NRF52X
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depends on SOC_NRF52832 || SOC_NRF52840
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help
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P0.9 and P0.10 are usually reserved for NFC. This option switch
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them to normal GPIO mode. HW enabling happens once in the device
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@ -223,5 +228,5 @@ config GPIO_AS_PINRESET
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config NRF_ENABLE_ICACHE
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bool "Enable the instruction cache (I-Cache)"
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depends on SOC_SERIES_NRF52X
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depends on SOC_NRF52832 || SOC_NRF52840
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default y
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@ -14,6 +14,10 @@
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#define REGION_FLASH_SIZE REGION_64K
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#elif CONFIG_FLASH_SIZE == 128
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#define REGION_FLASH_SIZE REGION_128K
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#elif CONFIG_FLASH_SIZE == 192
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#define REGION_FLASH_SIZE REGION_128K
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#define REGION_FLASH_1_SIZE REGION_64K
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#define REGION_FLASH_1_START CONFIG_FLASH_BASE_ADDRESS + KB(128)
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#elif CONFIG_FLASH_SIZE == 256
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#define REGION_FLASH_SIZE REGION_256K
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#elif CONFIG_FLASH_SIZE == 512
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@ -27,7 +31,11 @@
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#endif
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/* SRAM Region Definitions */
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#if CONFIG_SRAM_SIZE == 32
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#if CONFIG_SRAM_SIZE == 24
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#define REGION_SRAM_0_SIZE REGION_16K
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#define REGION_SRAM_1_SIZE REGION_8K
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#define REGION_SRAM_1_START CONFIG_SRAM_BASE_ADDRESS + KB(16)
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#elif CONFIG_SRAM_SIZE == 32
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#define REGION_SRAM_0_SIZE REGION_32K
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#elif CONFIG_SRAM_SIZE == 64
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#define REGION_SRAM_0_SIZE REGION_64K
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@ -18,10 +18,21 @@ static struct arm_mpu_region mpu_regions[] = {
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MPU_REGION_ENTRY("FLASH_0",
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CONFIG_FLASH_BASE_ADDRESS,
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REGION_FLASH_ATTR(REGION_FLASH_SIZE)),
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#if defined(REGION_FLASH_1_SIZE)
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MPU_REGION_ENTRY("FLASH_1",
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REGION_FLASH_1_START,
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REGION_FLASH_ATTR(REGION_FLASH_1_SIZE)),
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#endif /* REGION_FLASH_1_SIZE */
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/* Region 1 */
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MPU_REGION_ENTRY("SRAM_0",
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CONFIG_SRAM_BASE_ADDRESS,
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REGION_RAM_ATTR(REGION_SRAM_0_SIZE)),
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#if defined(REGION_SRAM_1_SIZE)
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MPU_REGION_ENTRY("SRAM_1",
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REGION_SRAM_1_START,
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REGION_RAM_ATTR(REGION_SRAM_1_SIZE)),
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#endif /* REGION_SRAM_1_SIZE */
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};
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struct arm_mpu_config mpu_config = {
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@ -25,7 +25,9 @@ extern void _NmiInit(void);
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#define NMI_INIT()
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#endif
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#if defined(CONFIG_SOC_NRF52832)
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#if defined(CONFIG_SOC_NRF52810)
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#include <system_nrf52810.h>
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#elif defined(CONFIG_SOC_NRF52832)
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#include <system_nrf52.h>
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#elif defined(CONFIG_SOC_NRF52840)
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#include <system_nrf52840.h>
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@ -6,4 +6,5 @@
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config BOARD_NRF52810_PCA10040
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bool "nRF52810 PCA10040"
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select HAS_DTS_GPIO
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depends on SOC_NRF52810_QFAA
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@ -24,6 +24,14 @@
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};
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};
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&gpiote {
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status ="ok";
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};
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&gpio0 {
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status ="ok";
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};
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&uart0 {
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status = "ok";
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current-speed = <115200>;
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@ -17,6 +17,9 @@
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#elif defined(CONFIG_SOC_NRF51822_QFAC)
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#define DT_FLASH_SIZE __SIZE_K(256)
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#define DT_SRAM_SIZE __SIZE_K(32)
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#elif defined(CONFIG_SOC_NRF52810_QFAA)
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#define DT_FLASH_SIZE __SIZE_K(192)
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#define DT_SRAM_SIZE __SIZE_K(24)
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#elif defined(CONFIG_SOC_NRF52832_QFAA)
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#define DT_FLASH_SIZE __SIZE_K(512)
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#define DT_SRAM_SIZE __SIZE_K(64)
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91
dts/arm/nordic/nrf52810.dtsi
Normal file
91
dts/arm/nordic/nrf52810.dtsi
Normal file
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#include <arm/armv7-m.dtsi>
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#include <dt-bindings/i2c/i2c.h>
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#include <nordic/mem.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m4";
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reg = <0>;
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};
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};
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flash-controller@4001E000 {
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compatible = "nrf,nrf52-flash-controller";
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reg = <0x4001E000 0x550>;
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#address-cells = <1>;
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#size-cells = <1>;
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label="NRF_FLASH_DRV_NAME";
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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label = "NRF_FLASH";
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reg = <0x00000000 DT_FLASH_SIZE>;
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write-block-size = <4>;
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};
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};
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sram0: memory@20000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SRAM_SIZE>;
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};
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soc {
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uart0: uart@40002000 {
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compatible = "nordic,nrf-uarte";
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reg = <0x40002000 0x1000>;
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interrupts = <2 1>;
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status = "disabled";
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label = "UART_0";
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};
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gpiote: gpiote@40006000 {
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compatible = "nordic,nrf5-gpiote";
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reg = <0x40006000 0x1000>;
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interrupts = <6 5>;
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interrupt-names = "gpiote";
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status = "disabled";
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label = "GPIOTE_0";
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};
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gpio0: gpio@50000000 {
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compatible = "nordic,nrf5-gpio";
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gpio-controller;
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reg = <0x50000000 0x200
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0x50000500 0x300>;
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#gpio-cells = <2>;
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label = "GPIO_0";
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status = "disabled";
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};
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i2c0: i2c@40003000 {
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compatible = "nordic,nrf5-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003000 0x1000>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupts = <3 1>;
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status = "disabled";
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label = "I2C_0";
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};
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wdt: watchdog@40010000 {
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compatible = "nordic,nrf-watchdog";
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reg = <0x40010000 0x1000>;
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interrupts = <16 1>;
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interrupt-names = "wdt";
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label = "WDT";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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