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arch: arm: nrf: Add support for the nRF52810

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The nRF52810 is a low-cost variant of the nRF52832, with a reduced set
of peripherals and memory. This commit adds basic support for it in the
arch SoC and dts folders.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Ioannis Glaropoulos <ioannis.glaropoulos@nordicsemi.no>
This commit is contained in:
Carles Cufi 2018-05-23 22:55:40 +02:00 • committed by Carles Cufí
commit 0f6bd5c891
10 changed files with 154 additions and 4 deletions
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1
arch/arm/soc/nordic_nrf/nrf52/CMakeLists.txt
View file

@ -1,3 +1,4 @@
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF52810 NRF52810_XXAA)
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF52832 NRF52832_XXAA)
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF52840 NRF52840_XXAA)

20
arch/arm/soc/nordic_nrf/nrf52/Kconfig.defconfig.nrf52810_QFAA Normal file
View file

@ -0,0 +1,20 @@
# Kconfig.defconfig.nrf52810 - Nordic Semiconductor nRF52810 MCU
#
# Copyright (c) 2018 Nordic Semiconductor ASA
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_NRF52810_QFAA
config SOC
string
default "nRF52810_QFAA"
config NUM_IRQS
int
default 30
endif # SOC_NRF52810_QFAA

9
arch/arm/soc/nordic_nrf/nrf52/Kconfig.soc
View file

@ -180,6 +180,11 @@ choice
prompt "nRF52x MCU Selection"
depends on SOC_SERIES_NRF52X
config SOC_NRF52810_QFAA
bool "NRF52810_QFAA"
select SOC_NRF52810
select HAS_SEGGER_RTT
config SOC_NRF52832_QFAA
bool "NRF52832_QFAA"
select SOC_NRF52832
@ -207,7 +212,7 @@ config ARM_MPU_NRF52X
config NFCT_PINS_AS_GPIOS
bool "NFCT pins as GPIOs"
depends on SOC_SERIES_NRF52X
depends on SOC_NRF52832 || SOC_NRF52840
help
P0.9 and P0.10 are usually reserved for NFC. This option switch
them to normal GPIO mode. HW enabling happens once in the device
@ -223,5 +228,5 @@ config GPIO_AS_PINRESET
config NRF_ENABLE_ICACHE
bool "Enable the instruction cache (I-Cache)"
depends on SOC_SERIES_NRF52X
depends on SOC_NRF52832 || SOC_NRF52840
default y

10
arch/arm/soc/nordic_nrf/nrf52/mpu_mem_cfg.h
View file

@ -14,6 +14,10 @@
#define REGION_FLASH_SIZE REGION_64K
#elif CONFIG_FLASH_SIZE == 128
#define REGION_FLASH_SIZE REGION_128K
#elif CONFIG_FLASH_SIZE == 192
#define REGION_FLASH_SIZE REGION_128K
#define REGION_FLASH_1_SIZE REGION_64K
#define REGION_FLASH_1_START CONFIG_FLASH_BASE_ADDRESS + KB(128)
#elif CONFIG_FLASH_SIZE == 256
#define REGION_FLASH_SIZE REGION_256K
#elif CONFIG_FLASH_SIZE == 512
@ -27,7 +31,11 @@
#endif
/* SRAM Region Definitions */
#if CONFIG_SRAM_SIZE == 32
#if CONFIG_SRAM_SIZE == 24
#define REGION_SRAM_0_SIZE REGION_16K
#define REGION_SRAM_1_SIZE REGION_8K
#define REGION_SRAM_1_START CONFIG_SRAM_BASE_ADDRESS + KB(16)
#elif CONFIG_SRAM_SIZE == 32
#define REGION_SRAM_0_SIZE REGION_32K
#elif CONFIG_SRAM_SIZE == 64
#define REGION_SRAM_0_SIZE REGION_64K

11
arch/arm/soc/nordic_nrf/nrf52/mpu_regions.c
View file

@ -18,10 +18,21 @@ static struct arm_mpu_region mpu_regions[] = {
MPU_REGION_ENTRY("FLASH_0",
CONFIG_FLASH_BASE_ADDRESS,
REGION_FLASH_ATTR(REGION_FLASH_SIZE)),
#if defined(REGION_FLASH_1_SIZE)
MPU_REGION_ENTRY("FLASH_1",
REGION_FLASH_1_START,
REGION_FLASH_ATTR(REGION_FLASH_1_SIZE)),
#endif /* REGION_FLASH_1_SIZE */
/* Region 1 */
MPU_REGION_ENTRY("SRAM_0",
CONFIG_SRAM_BASE_ADDRESS,
REGION_RAM_ATTR(REGION_SRAM_0_SIZE)),
#if defined(REGION_SRAM_1_SIZE)
MPU_REGION_ENTRY("SRAM_1",
REGION_SRAM_1_START,
REGION_RAM_ATTR(REGION_SRAM_1_SIZE)),
#endif /* REGION_SRAM_1_SIZE */
};
struct arm_mpu_config mpu_config = {

4
arch/arm/soc/nordic_nrf/nrf52/soc.c
View file

@ -25,7 +25,9 @@ extern void _NmiInit(void);
#define NMI_INIT()
#endif
#if defined(CONFIG_SOC_NRF52832)
#if defined(CONFIG_SOC_NRF52810)
#include <system_nrf52810.h>
#elif defined(CONFIG_SOC_NRF52832)
#include <system_nrf52.h>
#elif defined(CONFIG_SOC_NRF52840)
#include <system_nrf52840.h>

1
boards/arm/nrf52810_pca10040/Kconfig.board
View file

@ -6,4 +6,5 @@
config BOARD_NRF52810_PCA10040
bool "nRF52810 PCA10040"
select HAS_DTS_GPIO
depends on SOC_NRF52810_QFAA

8
boards/arm/nrf52810_pca10040/nrf52810_pca10040.dts
View file

@ -24,6 +24,14 @@
};
};
&gpiote {
status ="ok";
};
&gpio0 {
status ="ok";
};
&uart0 {
status = "ok";
current-speed = <115200>;

3
dts/arm/nordic/mem.h
View file

@ -17,6 +17,9 @@
#elif defined(CONFIG_SOC_NRF51822_QFAC)
#define DT_FLASH_SIZE __SIZE_K(256)
#define DT_SRAM_SIZE __SIZE_K(32)
#elif defined(CONFIG_SOC_NRF52810_QFAA)
#define DT_FLASH_SIZE __SIZE_K(192)
#define DT_SRAM_SIZE __SIZE_K(24)
#elif defined(CONFIG_SOC_NRF52832_QFAA)
#define DT_FLASH_SIZE __SIZE_K(512)
#define DT_SRAM_SIZE __SIZE_K(64)

91
dts/arm/nordic/nrf52810.dtsi Normal file
View file

@ -0,0 +1,91 @@
#include <arm/armv7-m.dtsi>
#include <dt-bindings/i2c/i2c.h>
#include <nordic/mem.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m4";
reg = <0>;
};
};
flash-controller@4001E000 {
compatible = "nrf,nrf52-flash-controller";
reg = <0x4001E000 0x550>;
#address-cells = <1>;
#size-cells = <1>;
label="NRF_FLASH_DRV_NAME";
flash0: flash@0 {
compatible = "soc-nv-flash";
label = "NRF_FLASH";
reg = <0x00000000 DT_FLASH_SIZE>;
write-block-size = <4>;
};
};
sram0: memory@20000000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x20000000 DT_SRAM_SIZE>;
};
soc {
uart0: uart@40002000 {
compatible = "nordic,nrf-uarte";
reg = <0x40002000 0x1000>;
interrupts = <2 1>;
status = "disabled";
label = "UART_0";
};
gpiote: gpiote@40006000 {
compatible = "nordic,nrf5-gpiote";
reg = <0x40006000 0x1000>;
interrupts = <6 5>;
interrupt-names = "gpiote";
status = "disabled";
label = "GPIOTE_0";
};
gpio0: gpio@50000000 {
compatible = "nordic,nrf5-gpio";
gpio-controller;
reg = <0x50000000 0x200
0x50000500 0x300>;
#gpio-cells = <2>;
label = "GPIO_0";
status = "disabled";
};
i2c0: i2c@40003000 {
compatible = "nordic,nrf5-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003000 0x1000>;
clock-frequency = <I2C_BITRATE_STANDARD>;
interrupts = <3 1>;
status = "disabled";
label = "I2C_0";
};
wdt: watchdog@40010000 {
compatible = "nordic,nrf-watchdog";
reg = <0x40010000 0x1000>;
interrupts = <16 1>;
interrupt-names = "wdt";
label = "WDT";
};
};
};
&nvic {
arm,num-irq-priority-bits = <3>;
};