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soc: stm32l4xx: add support for STM32L475XG

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Add support for STM32L475xG SoC as a preliminary for
Discovery IOT board support.
stm32l476.dtsi file is now including stm32l475.dtsi
since STM32L476 SoC is a STM32L475 SoC with LCD support

Change-Id: I7567255e4172231cbf4899474617ecae0cd68d64
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2017-04-26 15:23:04 +02:00 • committed by Kumar Gala
commit eee56a7c10
5 changed files with 85 additions and 53 deletions
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18
arch/arm/soc/st_stm32/stm32l4/Kconfig.defconfig.stm32l475xg Normal file
View file

@ -0,0 +1,18 @@
# Kconfig - ST Microelectronics STM32L475xG MCU
#
# Copyright (c) 2017 Linaro Limited
#
# SPDX-License-Identifier: Apache-2.0
#
if SOC_STM32L475XG
config SOC
string
default stm32l475xx
config NUM_IRQS
int
default 82
endif # SOC_STM32L475XG

4
arch/arm/soc/st_stm32/stm32l4/Kconfig.soc
View file

@ -14,4 +14,8 @@ config SOC_STM32L476XX
bool "STM32L476XX"
select HAS_STM32CUBE
config SOC_STM32L475XG
bool "STM32L475XG"
select HAS_STM32CUBE
endchoice

3
dts/arm/st/mem.h
View file

@ -33,6 +33,9 @@
#elif defined(CONFIG_SOC_STM32F429XX)
#define DT_FLASH_SIZE __SIZE_K(2048)
#define DT_SRAM_SIZE __SIZE_K(256)
#elif defined(CONFIG_SOC_STM32L475XG)
#define DT_FLASH_SIZE __SIZE_K(1024)
#define DT_SRAM_SIZE __SIZE_K(96)
#elif defined(CONFIG_SOC_STM32L476XX)
#define DT_FLASH_SIZE __SIZE_K(1024)
#define DT_SRAM_SIZE __SIZE_K(96)

59
dts/arm/st/stm32l475.dtsi Normal file
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@ -0,0 +1,59 @@
/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <st/mem.h>
/ {
flash0: flash {
reg = <0x08000000 DT_FLASH_SIZE>;
};
sram0: memory {
reg = <0x20000000 DT_SRAM_SIZE>;
};
soc {
usart1: uart@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
interrupts = <37 0>;
status = "disabled";
};
usart2: uart@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
interrupts = <38 0>;
status = "disabled";
};
usart3: uart@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
interrupts = <39 0>;
status = "disabled";
};
uart4: uart@40004c00 {
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
interrupts = <52 0>;
status = "disabled";
};
uart5: uart@40005000 {
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
interrupts = <53 0>;
status = "disabled";
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};

54
dts/arm/st/stm32l476.dtsi
View file

@ -4,56 +4,4 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <st/mem.h>
/ {
flash0: flash {
reg = <0x08000000 DT_FLASH_SIZE>;
};
sram0: memory {
reg = <0x20000000 DT_SRAM_SIZE>;
};
soc {
usart1: uart@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
interrupts = <37 0>;
status = "disabled";
};
usart2: uart@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
interrupts = <38 0>;
status = "disabled";
};
usart3: uart@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
interrupts = <39 0>;
status = "disabled";
};
uart4: uart@40004c00 {
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
interrupts = <52 0>;
status = "disabled";
};
uart5: uart@40005000 {
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
interrupts = <53 0>;
status = "disabled";
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};
#include <st/stm32l475.dtsi>