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arm: dts: st: Convert STM32F1 based boards to dts

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Converted over all STM32F1 based boards to use device tree and removed
associated bits that now come from the device tree for STM32F1.  Also
renamed the STM32F10{3,7} SoC dtsi to try and make it clear that the 'X'
is a place holder.  Fixedup the top level compatiables in the boards to
be the specific 'X' instead of the generic one.

Boards that are now using devicetree:
* Nucleo f103rb
* STM3210C Eval
* STM32 MINI A15

Change-Id: I29b3634ec7451f974687d55980414efa655e2e96
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2017-04-05 11:22:20 -05:00
commit 51ccb58dbb
17 changed files with 62 additions and 35 deletions
Download patch file Download diff file Expand all files Collapse all files

6
arch/arm/soc/st_stm32/stm32f1/Kconfig.defconfig.series
View file

@ -12,12 +12,6 @@ source "arch/arm/soc/st_stm32/stm32f1/Kconfig.defconfig.stm32f1*"
config SOC_SERIES
default stm32f1
if !HAS_DTS
config NUM_IRQ_PRIO_BITS
int
default 4
endif # !HAS_DTS
if WATCHDOG
config IWDG_STM32

8
arch/arm/soc/st_stm32/stm32f1/Kconfig.defconfig.stm32f103xb
View file

@ -11,14 +11,6 @@ config SOC
string
default stm32f103xb
if !HAS_DTS
config SRAM_SIZE
default 20
config FLASH_SIZE
default 128
endif # !HAS_DTS
config NUM_IRQS
int
default 59

6
arch/arm/soc/st_stm32/stm32f1/Kconfig.defconfig.stm32f103xe
View file

@ -11,12 +11,6 @@ config SOC
string
default stm32f103xe
config SRAM_SIZE
default 64
config FLASH_SIZE
default 512
config NUM_IRQS
int
default 68

6
arch/arm/soc/st_stm32/stm32f1/Kconfig.defconfig.stm32f107xc
View file

@ -11,12 +11,6 @@ config SOC
string
default stm32f107xc
config SRAM_SIZE
default 64
config FLASH_SIZE
default 256
config NUM_IRQS
int
default 68

4
boards/arm/nucleo_f103rb/nucleo_f103rb_defconfig
View file

@ -12,7 +12,6 @@ CONFIG_SERIAL=y
CONFIG_UART_STM32=y
# enable USART2 - passthrough to STLINK v2 connector
CONFIG_UART_STM32_PORT_2=y
CONFIG_UART_STM32_PORT_2_BAUD_RATE=115200
# enable console on this port by default
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
@ -49,3 +48,6 @@ CONFIG_CLOCK_STM32F10X_APB2_PRESCALER=0
CONFIG_PWM=y
CONFIG_PWM_STM32=y
CONFIG_PWM_STM32_1=y
#enable DTS
CONFIG_HAS_DTS=y

1
boards/arm/olimexino_stm32/olimexino_stm32_defconfig
View file

@ -12,7 +12,6 @@ CONFIG_SERIAL=y
CONFIG_UART_STM32=y
# enable USART1
CONFIG_UART_STM32_PORT_1=y
CONFIG_UART_STM32_PORT_1_BAUD_RATE=115200
# enable console on this port by default
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y

4
boards/arm/stm3210c_eval/stm3210c_eval_defconfig
View file

@ -24,7 +24,6 @@ CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_STM32=y
# enable USART2 - passthrough to STLINK v2 connector
CONFIG_UART_STM32_PORT_2=y
CONFIG_UART_STM32_PORT_2_BAUD_RATE=115200
# enable console on this port by default
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
@ -59,3 +58,6 @@ CONFIG_CLOCK_STM32F10X_CONN_LINE_AHB_PRESCALER=0
# APB1 clock must not to exceed 36MHz limit
CONFIG_CLOCK_STM32F10X_CONN_LINE_APB1_PRESCALER=2
CONFIG_CLOCK_STM32F10X_CONN_LINE_APB2_PRESCALER=0
#enable DTS
CONFIG_HAS_DTS=y

4
boards/arm/stm32_mini_a15/stm32_mini_a15_defconfig
View file

@ -11,7 +11,6 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
CONFIG_SERIAL=y
CONFIG_UART_STM32=y
CONFIG_UART_STM32_PORT_1=y
CONFIG_UART_STM32_PORT_1_BAUD_RATE=115200
# enable pinmux
CONFIG_PINMUX=y
@ -38,3 +37,6 @@ CONFIG_CLOCK_STM32F10X_APB2_PRESCALER=0
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
#enable DTS
CONFIG_HAS_DTS=y

3
dts/arm/Makefile
View file

@ -9,6 +9,9 @@ dtb-$(CONFIG_BOARD_OLIMEXINO_STM32) = olimexino_stm32.dts_compiled
dtb-$(CONFIG_BOARD_96B_CARBON) = 96b_carbon.dts_compiled
dtb-$(CONFIG_BOARD_NUCLEO_F401RE) = nucleo_f401re.dts_compiled
dtb-$(CONFIG_BOARD_NUCLEO_F411RE) = nucleo_f411re.dts_compiled
dtb-$(CONFIG_BOARD_NUCLEO_F103RB) = nucleo_f103rb.dts_compiled
dtb-$(CONFIG_BOARD_STM3210C_EVAL) = stm3210c_eval.dts_compiled
dtb-$(CONFIG_BOARD_STM32_MINI_A15) = stm32_mini_a15.dts_compiled
always := $(dtb-y)
endif

2
dts/arm/nucleo_f103rb.dts
View file

@ -5,7 +5,7 @@
*/
/dts-v1/;
#include <st/stm32f103rb.dtsi>
#include <st/stm32f103Xb.dtsi>
/ {
model = "STMicroelectronics STM32F103RB-NUCLEO board";

13
dts/arm/nucleo_f103rb.fixup Normal file
View file

@ -0,0 +1,13 @@
/* This file is a temporary workaround for mapping of the generated information
* to the current driver definitions. This will be removed when the drivers
* are modified to handle the generated information, or the mapping of
* generated data matches the driver definitions.
*/
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define CONFIG_UART_STM32_PORT_2_BASE_ADDRESS ST_STM32_USART_40004400_BASE_ADDRESS
#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_BAUD_RATE
#define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY
#define PORT_2_IRQ ST_STM32_USART_40004400_IRQ_0

4
dts/arm/olimexino_stm32.dts
View file

@ -5,11 +5,11 @@
*/
/dts-v1/;
#include <st/stm32f103xb.dtsi>
#include <st/stm32f103Xb.dtsi>
/ {
model = "Olimex OLIMEXINO-STM32 board";
compatible = "st,olimexino_stm32", "st,stm32f103xb";
compatible = "st,olimexino_stm32", "st,stm32f103rb";
chosen {
zephyr,console = &usart1;

3
dts/arm/st/stm32f103xe.dtsi → dts/arm/st/stm32f103Xb.dtsi
View file

@ -1,6 +1,9 @@
/*
* Copyright (c) 2017 I-SENSE group of ICCS
*
* SoC device tree include for STM32F103xB SoCs
* where 'x' is replaced for specific SoCs like {C,R,T,V}
*
* SPDX-License-Identifier: Apache-2.0
*/

3
dts/arm/st/stm32f103xb.dtsi → dts/arm/st/stm32f103Xe.dtsi
View file

@ -1,6 +1,9 @@
/*
* Copyright (c) 2017 I-SENSE group of ICCS
*
* SoC device tree include for STM32F103xE SoCs
* where 'x' is replaced for specific SoCs like {R,V,Z}
*
* SPDX-License-Identifier: Apache-2.0
*/

13
dts/arm/stm3210c_eval.fixup Normal file
View file

@ -0,0 +1,13 @@
/* This file is a temporary workaround for mapping of the generated information
* to the current driver definitions. This will be removed when the drivers
* are modified to handle the generated information, or the mapping of
* generated data matches the driver definitions.
*/
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define CONFIG_UART_STM32_PORT_2_BASE_ADDRESS ST_STM32_USART_40004400_BASE_ADDRESS
#define CONFIG_UART_STM32_PORT_2_BAUD_RATE ST_STM32_USART_40004400_BAUD_RATE
#define CONFIG_UART_STM32_PORT_2_IRQ_PRI ST_STM32_USART_40004400_IRQ_0_PRIORITY
#define PORT_2_IRQ ST_STM32_USART_40004400_IRQ_0

4
dts/arm/stm32_mini_a15.dts
View file

@ -5,11 +5,11 @@
*/
/dts-v1/;
#include <st/stm32f103xe.dtsi>
#include <st/stm32f103Xe.dtsi>
/ {
model = "STM32 MINI A15 board";
compatible = "st,stm32_mini_a15", "st,stm32f103xe";
compatible = "st,stm32_mini_a15", "st,stm32f103ve";
chosen {
zephyr,console = &usart1;

13
dts/arm/stm32_mini_a15.fixup Normal file
View file

@ -0,0 +1,13 @@
/* This file is a temporary workaround for mapping of the generated information
* to the current driver definitions. This will be removed when the drivers
* are modified to handle the generated information, or the mapping of
* generated data matches the driver definitions.
*/
#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
#define CONFIG_UART_STM32_PORT_1_BASE_ADDRESS ST_STM32_USART_40013800_BASE_ADDRESS
#define CONFIG_UART_STM32_PORT_1_BAUD_RATE ST_STM32_USART_40013800_BAUD_RATE
#define CONFIG_UART_STM32_PORT_1_IRQ_PRI ST_STM32_USART_40013800_IRQ_0_PRIORITY
#define PORT_1_IRQ ST_STM32_USART_40013800_IRQ_0