arm: Add Cypress PSoC6 SoC support
Added initial support and created the corresponding device tree part for building PSoC6 SoC as part of Zephyr. Signed-off-by: Nazar Chornenkyy <nazar.chornenkyy@cypress.com> Signed-off-by: Oleg Kapshii <oleg.kapshii@cypress.com>
This commit is contained in:
Nazar Chornenkyy
Anas Nashif
parent
4d6b662149
commit
93f938c44e
18 changed files with 792 additions and 0 deletions
89
dts/arm/cypress/psoc6.dtsi
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89
dts/arm/cypress/psoc6.dtsi
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@ -0,0 +1,89 @@
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/*
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* Copyright (c) 2018, Cypress
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m0+";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-m4f";
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reg = <1>;
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};
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};
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flash-controller@40250000 {
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compatible = "cypress,psoc6-flash-controller";
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reg = <0x40250000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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label="CYPRESS_FLASH_DRV_NAME";
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flash0: flash@10000000 {
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compatible = "soc-nv-flash";
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label = "FLASH_0";
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reg = <0x10000000 DT_SIZE_K(384)>;
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write-block-size = <4>;
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};
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flash1: flash@10060000 {
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compatible = "soc-nv-flash";
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label = "FLASH_1";
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reg = <0x10060000 DT_SIZE_K(640)>;
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write-block-size = <4>;
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};
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};
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sram0: memory@8000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x08000000 DT_SIZE_K(140)>;
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};
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sram1: memory@8023000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x08023000 DT_SIZE_K(4)>;
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};
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sram2: memory@8024000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x08024000 DT_SIZE_K(112)>;
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};
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soc {
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uart5: uart@40660000 {
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compatible = "cypress,psoc6-uart";
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reg = <0x40660000 0x10000>;
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interrupts = <2 1>;
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status = "disabled";
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label = "uart_5";
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};
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uart6: uart@40670000 {
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compatible = "cypress,psoc6-uart";
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reg = <0x40670000 0x10000>;
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interrupts = <2 1>;
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status = "disabled";
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label = "uart_6";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <2>;
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};
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22
dts/arm/cypress/psoc6_cm0.dtsi
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22
dts/arm/cypress/psoc6_cm0.dtsi
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@ -0,0 +1,22 @@
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/*
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* Copyright (c) 2018, Cypress
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv6-m.dtsi>
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#include <cypress/psoc6.dtsi>
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/ {
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cpus {
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cpu@0 {
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compatible = "arm,cortex-m0+";
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};
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/delete-node/ cpu@1;
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <2>;
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};
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22
dts/arm/cypress/psoc6_cm4.dtsi
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22
dts/arm/cypress/psoc6_cm4.dtsi
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@ -0,0 +1,22 @@
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/*
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* Copyright (c) 2018, Cypress
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <cypress/psoc6.dtsi>
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/ {
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cpus {
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/delete-node/ cpu@0;
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cpu@1 {
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compatible = "arm,cortex-m4f";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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@ -0,0 +1,21 @@
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#
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# Copyright (c) 2018, Cypress
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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---
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title: Cypress Flash Controller
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id: cypress,psoc6-flash-controller
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version: 0.1
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description: >
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This binding gives a base representation of the Cypress Flash Controller
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inherits:
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!include flash-controller.yaml
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properties:
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compatible:
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constraint: "cypress,psoc6-flash-controller"
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...
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7
soc/arm/cypress/CMakeLists.txt
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7
soc/arm/cypress/CMakeLists.txt
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@ -0,0 +1,7 @@
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#
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# Copyright (c) 2018, Cypress
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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add_subdirectory(${SOC_SERIES})
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34
soc/arm/cypress/Kconfig
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34
soc/arm/cypress/Kconfig
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@ -0,0 +1,34 @@
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#
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# Copyright (c) 2018, Cypress
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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choice
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prompt "Cypress PSoC6 MCU Selection"
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depends on SOC_SERIES_PSOC62
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config SOC_PSOC6_M0
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bool "SOC_PSOC6_M0"
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select CPU_CORTEX_M0PLUS
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select CPU_CORTEX_M_HAS_VTOR
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config SOC_PSOC6_M4
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bool "SOC_PSOC6_M4"
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select CPU_CORTEX_M4
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endchoice
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config SOC_FAMILY_PSOC6
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bool
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# omit prompt to signify a "hidden" option
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default n
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if SOC_FAMILY_PSOC6
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config SOC_FAMILY
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string
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default "cypress"
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source "soc/arm/cypress/*/Kconfig.soc"
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endif # SOC_FAMILY_PSOC6
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7
soc/arm/cypress/Kconfig.defconfig
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7
soc/arm/cypress/Kconfig.defconfig
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#
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# Copyright (c) 2018, Cypress
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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gsource "soc/arm/cypress/*/Kconfig.defconfig.series"
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7
soc/arm/cypress/Kconfig.soc
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7
soc/arm/cypress/Kconfig.soc
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#
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# Copyright (c) 2018, Cypress
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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source "soc/arm/cypress/*/Kconfig.series"
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10
soc/arm/cypress/psoc6/CMakeLists.txt
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10
soc/arm/cypress/psoc6/CMakeLists.txt
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#
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# Copyright (c) 2018, Cypress
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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zephyr_include_directories(.)
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zephyr_sources(
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soc.c
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)
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21
soc/arm/cypress/psoc6/Kconfig.defconfig.psoc6_m0
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21
soc/arm/cypress/psoc6/Kconfig.defconfig.psoc6_m0
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# Kconfig - Cypress PSoC6 CM0 platform configuration options
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#
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# Copyright (c) 2018, Cypress
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_PSOC6_M0
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config SOC
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string
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default "psoc6_m0"
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if SERIAL
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config UART_PSOC6
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def_bool y
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endif # SERIAL
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endif # SOC_PSOC6_M0
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21
soc/arm/cypress/psoc6/Kconfig.defconfig.psoc6_m4
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21
soc/arm/cypress/psoc6/Kconfig.defconfig.psoc6_m4
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# Kconfig - Cypress PSoC6 CM4 platform configuration options
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#
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# Copyright (c) 2018, Cypress
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_PSOC6_M4
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config SOC
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string
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default "psoc6_m4"
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if SERIAL
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config UART_PSOC6
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def_bool y
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endif # SERIAL
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endif # SOC_PSOC6_M4
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29
soc/arm/cypress/psoc6/Kconfig.defconfig.series
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29
soc/arm/cypress/psoc6/Kconfig.defconfig.series
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# Kconfig.defconfig.series - Cypress Semiconductor PSoC6 series configuration
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# options
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#
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# Copyright (c) 2018, Cypress
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_SERIES_PSOC62
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config SOC_SERIES
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default "psoc6"
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config SOC_PART_NUMBER
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string
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default "CY8C6247BZI_D54" if SOC_PART_NUMBER_CY8C6247BZI_D54
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config NUM_IRQS
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int
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# must be >= the highest interrupt number used
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default 40
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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int
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default 50000000
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source "soc/arm/cypress/psoc6/Kconfig.defconfig.psoc*"
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endif # SOC_SERIES_PSOC62
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15
soc/arm/cypress/psoc6/Kconfig.series
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15
soc/arm/cypress/psoc6/Kconfig.series
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# Kconfig.series - Cypress PSoC6 MCU line
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#
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# Copyright (c) 2018, Cypress Semiconductor
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config SOC_SERIES_PSOC62
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bool "Cypress PSoC6 series MCU"
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select SOC_FAMILY_PSOC6
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select SYS_POWER_LOW_POWER_STATE_SUPPORTED
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select CPU_HAS_SYSTICK
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select HAS_CYPRESS_DRIVERS
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help
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Enable support for Cypress PSoC6 MCU series
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15
soc/arm/cypress/psoc6/Kconfig.soc
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15
soc/arm/cypress/psoc6/Kconfig.soc
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# Kconfig.soc - Cypress PSOC6 MCU line
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#
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# Copyright (c) 2018, Cypress
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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choice
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prompt "Cypress PSoC6 MCU Selection"
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depends on SOC_SERIES_PSOC62
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config SOC_PART_NUMBER_CY8C6247BZI_D54
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bool "CY8C6247BZI_D54"
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endchoice
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48
soc/arm/cypress/psoc6/dts.fixup
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48
soc/arm/cypress/psoc6/dts.fixup
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/*
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* Copyright (c) 2018, Cypress
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* SoC level DTS fixup file */
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#if defined(CONFIG_SOC_PSOC6_M0)
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#else
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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#endif
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#define CONFIG_UART_PSOC6_UART_5_NAME "uart_5"
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#define CONFIG_UART_PSOC6_UART_5_BASE_ADDRESS SCB5
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#define CONFIG_UART_PSOC6_UART_5_PORT P5_0_PORT
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#define CONFIG_UART_PSOC6_UART_5_RX_NUM P5_0_NUM
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#define CONFIG_UART_PSOC6_UART_5_TX_NUM P5_1_NUM
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#define CONFIG_UART_PSOC6_UART_5_RX_VAL P5_0_SCB5_UART_RX
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#define CONFIG_UART_PSOC6_UART_5_TX_VAL P5_1_SCB5_UART_TX
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#define CONFIG_UART_PSOC6_UART_5_CLOCK PCLK_SCB5_CLOCK
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#define CONFIG_UART_PSOC6_UART_6_NAME "uart_6"
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#define CONFIG_UART_PSOC6_UART_6_BASE_ADDRESS SCB6
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#define CONFIG_UART_PSOC6_UART_6_PORT P12_0_PORT
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#define CONFIG_UART_PSOC6_UART_6_RX_NUM P12_0_NUM
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#define CONFIG_UART_PSOC6_UART_6_TX_NUM P12_1_NUM
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#define CONFIG_UART_PSOC6_UART_6_RX_VAL P12_0_SCB6_UART_RX
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#define CONFIG_UART_PSOC6_UART_6_TX_VAL P12_1_SCB6_UART_TX
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#define CONFIG_UART_PSOC6_UART_6_CLOCK PCLK_SCB6_CLOCK
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/* UART desired baud rate is 115200 bps (Standard mode).
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* The UART baud rate = (SCB clock frequency / Oversample).
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* For PeriClk = 50 MHz, select divider value 36 and get SCB clock = (50 MHz / 36) = 1,389 MHz.
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* Select Oversample = 12. These setting results UART data rate = 1,389 MHz / 12 = 115750 bps.
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*/
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#define CONFIG_UART_PSOC6_CONFIG_OVERSAMPLE (12UL)
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#define CONFIG_UART_PSOC6_CONFIG_BREAKWIDTH (11UL)
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#define CONFIG_UART_PSOC6_CONFIG_DATAWIDTH (8UL)
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/* Assign divider type and number for UART */
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#define CONFIG_UART_PSOC6_UART_CLK_DIV_TYPE (CY_SYSCLK_DIV_8_BIT)
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#define CONFIG_UART_PSOC6_UART_CLK_DIV_NUMBER (PERI_DIV_8_NR - 1u)
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#define CONFIG_UART_PSOC6_UART_CLK_DIV_VAL (35UL)
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/* End of SoC Level DTS fixup file */
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16
soc/arm/cypress/psoc6/linker.ld
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16
soc/arm/cypress/psoc6/linker.ld
Normal file
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/*
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* Copyright (c) 2018 Cypress
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Linker command/script file
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*
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* This is the linker script for both standard images and XIP images.
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*/
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#include <autoconf.h>
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#include <arch/arm/cortex_m/scripts/linker.ld>
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380
soc/arm/cypress/psoc6/soc.c
Normal file
380
soc/arm/cypress/psoc6/soc.c
Normal file
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/*
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* Copyright (c) 2018, Cypress
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <device.h>
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#include <init.h>
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#include <arch/cpu.h>
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#include <cortex_m/exc.h>
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#include "cy_syslib.h"
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#include "cy_gpio.h"
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#include "cy_scb_uart.h"
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#include "cy_syslib.h"
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#include "cy_syspm.h"
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#include "cy_sysclk.h"
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#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
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#define CY_CFG_SYSCLK_FLL_ENABLED 1
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#define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
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#define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL
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#define CY_CFG_SYSCLK_ILO_ENABLED 1
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#define CY_CFG_SYSCLK_IMO_ENABLED 1
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#define CY_CFG_SYSCLK_CLKLF_ENABLED 1
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#define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
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#define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
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#define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
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#define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1
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#define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1
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#define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
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#define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
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#define CY_CFG_PWR_ENABLED 1
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#define CY_CFG_PWR_USING_LDO 1
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#define CY_CFG_PWR_USING_PMIC 0
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#define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_1_1V
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#define CY_CFG_PWR_VDDA_MV 3300
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#define CY_CFG_PWR_USING_ULP 0
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static const cy_stc_fll_manual_config_t srss_0__clock_0__fll_0__fllConfig = {
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.fllMult = 500u,
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.refDiv = 20u,
|
||||
.ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
|
||||
.enableOutputDiv = true,
|
||||
.lockTolerance = 10u,
|
||||
.igain = 9u,
|
||||
.pgain = 5u,
|
||||
.settlingCount = 8u,
|
||||
.outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
|
||||
.cco_Freq = 355u,
|
||||
};
|
||||
|
||||
static inline void Cy_SysClk_ClkFastInit(void)
|
||||
{
|
||||
Cy_SysClk_ClkFastSetDivider(0u);
|
||||
}
|
||||
static inline void Cy_SysClk_FllInit(void)
|
||||
{
|
||||
Cy_SysClk_FllManualConfigure(&srss_0__clock_0__fll_0__fllConfig);
|
||||
Cy_SysClk_FllEnable(200000u);
|
||||
}
|
||||
static inline void Cy_SysClk_ClkHf0Init(void)
|
||||
{
|
||||
Cy_SysClk_ClkHfSetSource(0u, CY_SYSCLK_CLKHF_IN_CLKPATH0);
|
||||
Cy_SysClk_ClkHfSetDivider(0u, CY_SYSCLK_CLKHF_NO_DIVIDE);
|
||||
Cy_SysClk_ClkHfEnable(0u);
|
||||
|
||||
}
|
||||
static inline void Cy_SysClk_IloInit(void)
|
||||
{
|
||||
Cy_SysClk_IloEnable();
|
||||
Cy_SysClk_IloHibernateOn(true);
|
||||
}
|
||||
static inline void Cy_SysClk_ClkLfInit(void)
|
||||
{
|
||||
Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_ILO);
|
||||
}
|
||||
static inline void Cy_SysClk_ClkPath0Init(void)
|
||||
{
|
||||
Cy_SysClk_ClkPathSetSource(0u, CY_SYSCLK_CLKPATH_IN_IMO);
|
||||
}
|
||||
static inline void Cy_SysClk_ClkPath1Init(void)
|
||||
{
|
||||
Cy_SysClk_ClkPathSetSource(1u, CY_SYSCLK_CLKPATH_IN_IMO);
|
||||
}
|
||||
static inline void Cy_SysClk_ClkPath2Init(void)
|
||||
{
|
||||
Cy_SysClk_ClkPathSetSource(2u, CY_SYSCLK_CLKPATH_IN_IMO);
|
||||
}
|
||||
static inline void Cy_SysClk_ClkPath3Init(void)
|
||||
{
|
||||
Cy_SysClk_ClkPathSetSource(3u, CY_SYSCLK_CLKPATH_IN_IMO);
|
||||
}
|
||||
static inline void Cy_SysClk_ClkPath4Init(void)
|
||||
{
|
||||
Cy_SysClk_ClkPathSetSource(4u, CY_SYSCLK_CLKPATH_IN_IMO);
|
||||
}
|
||||
static inline void Cy_SysClk_ClkPeriInit(void)
|
||||
{
|
||||
Cy_SysClk_ClkPeriSetDivider(1u);
|
||||
}
|
||||
static inline void Cy_SysClk_ClkSlowInit(void)
|
||||
{
|
||||
Cy_SysClk_ClkSlowSetDivider(0u);
|
||||
}
|
||||
|
||||
|
||||
static void init_cycfg_platform(void)
|
||||
{
|
||||
/* Set worst case memory wait states (! ultra low power, 150 MHz), will
|
||||
* update at the end
|
||||
*/
|
||||
Cy_SysLib_SetWaitStates(false, 150);
|
||||
#ifdef CY_CFG_PWR_ENABLED
|
||||
/* Configure power mode */
|
||||
#if CY_CFG_PWR_USING_LDO
|
||||
Cy_SysPm_LdoSetVoltage(CY_CFG_PWR_LDO_VOLTAGE);
|
||||
#else
|
||||
Cy_SysPm_BuckEnable(CY_CFG_PWR_SIMO_VOLTAGE);
|
||||
#endif
|
||||
/* Configure PMIC */
|
||||
Cy_SysPm_UnlockPmic();
|
||||
#if CY_CFG_PWR_USING_PMIC
|
||||
Cy_SysPm_PmicEnableOutput();
|
||||
#else
|
||||
Cy_SysPm_PmicDisableOutput();
|
||||
#endif
|
||||
#endif
|
||||
/* Enable all source clocks */
|
||||
#ifdef CY_CFG_SYSCLK_PILO_ENABLED
|
||||
Cy_SysClk_PiloInit();
|
||||
#endif
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_WCO_ENABLED
|
||||
Cy_SysClk_WcoInit();
|
||||
#endif
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
|
||||
Cy_SysClk_ClkLfInit();
|
||||
#endif
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
|
||||
Cy_SysClk_AltHfInit();
|
||||
#endif
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_ECO_ENABLED
|
||||
Cy_SysClk_EcoInit();
|
||||
#endif
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
|
||||
Cy_SysClk_ExtClkInit();
|
||||
#endif
|
||||
|
||||
/* Configure CPU clock dividers */
|
||||
#ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
|
||||
Cy_SysClk_ClkFastInit();
|
||||
#endif
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
|
||||
Cy_SysClk_ClkPeriInit();
|
||||
#endif
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
|
||||
Cy_SysClk_ClkSlowInit();
|
||||
#endif
|
||||
|
||||
/* Configure HF clocks */
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF0_ENABLED
|
||||
Cy_SysClk_ClkHf0Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
|
||||
Cy_SysClk_ClkHf1Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
|
||||
Cy_SysClk_ClkHf2Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
|
||||
Cy_SysClk_ClkHf3Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
|
||||
Cy_SysClk_ClkHf4Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
|
||||
Cy_SysClk_ClkHf5Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
|
||||
Cy_SysClk_ClkHf6Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
|
||||
Cy_SysClk_ClkHf7Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
|
||||
Cy_SysClk_ClkHf8Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
|
||||
Cy_SysClk_ClkHf9Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
|
||||
Cy_SysClk_ClkHf10Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
|
||||
Cy_SysClk_ClkHf11Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
|
||||
Cy_SysClk_ClkHf12Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
|
||||
Cy_SysClk_ClkHf13Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
|
||||
Cy_SysClk_ClkHf14Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
|
||||
Cy_SysClk_ClkHf15Init();
|
||||
#endif
|
||||
|
||||
/* Configure Path Clocks */
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
|
||||
Cy_SysClk_ClkPath0Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
|
||||
Cy_SysClk_ClkPath1Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
|
||||
Cy_SysClk_ClkPath2Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
|
||||
Cy_SysClk_ClkPath3Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
|
||||
Cy_SysClk_ClkPath4Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
|
||||
Cy_SysClk_ClkPath5Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
|
||||
Cy_SysClk_ClkPath6Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
|
||||
Cy_SysClk_ClkPath7Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
|
||||
Cy_SysClk_ClkPath8Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
|
||||
Cy_SysClk_ClkPath9Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
|
||||
Cy_SysClk_ClkPath10Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
|
||||
Cy_SysClk_ClkPath11Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
|
||||
Cy_SysClk_ClkPath12Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
|
||||
Cy_SysClk_ClkPath13Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
|
||||
Cy_SysClk_ClkPath14Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
|
||||
Cy_SysClk_ClkPath15Init();
|
||||
#endif
|
||||
|
||||
/* Configure and enable FLL */
|
||||
#ifdef CY_CFG_SYSCLK_FLL_ENABLED
|
||||
Cy_SysClk_FllInit();
|
||||
#endif
|
||||
|
||||
/* Configure and enable PLLs */
|
||||
#ifdef CY_CFG_SYSCLK_PLL0_ENABLED
|
||||
Cy_SysClk_Pll0Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL1_ENABLED
|
||||
Cy_SysClk_Pll1Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL2_ENABLED
|
||||
Cy_SysClk_Pll2Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL3_ENABLED
|
||||
Cy_SysClk_Pll3Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL4_ENABLED
|
||||
Cy_SysClk_Pll4Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL5_ENABLED
|
||||
Cy_SysClk_Pll5Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL6_ENABLED
|
||||
Cy_SysClk_Pll6Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL7_ENABLED
|
||||
Cy_SysClk_Pll7Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL8_ENABLED
|
||||
Cy_SysClk_Pll8Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL9_ENABLED
|
||||
Cy_SysClk_Pll9Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL10_ENABLED
|
||||
Cy_SysClk_Pll10Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL11_ENABLED
|
||||
Cy_SysClk_Pll11Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL12_ENABLED
|
||||
Cy_SysClk_Pll12Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL13_ENABLED
|
||||
Cy_SysClk_Pll13Init();
|
||||
#endif
|
||||
#ifdef CY_CFG_SYSCLK_PLL14_ENABLED
|
||||
Cy_SysClk_Pll14Init();
|
||||
#endif
|
||||
|
||||
/* Configure miscellaneous clocks */
|
||||
#ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
|
||||
Cy_SysClk_ClkTimerInit();
|
||||
#endif
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
|
||||
Cy_SysClk_ClkAltSysTickInit();
|
||||
#endif
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
|
||||
Cy_SysClk_ClkPumpInit();
|
||||
#endif
|
||||
|
||||
#ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
|
||||
Cy_SysClk_ClkBakInit();
|
||||
#endif
|
||||
|
||||
/* Configure default enabled clocks */
|
||||
#ifdef CY_CFG_SYSCLK_ILO_ENABLED
|
||||
Cy_SysClk_IloInit();
|
||||
#else
|
||||
Cy_SysClk_IloDisable();
|
||||
#endif
|
||||
|
||||
#ifndef CY_CFG_SYSCLK_IMO_ENABLED
|
||||
#error the IMO must be enabled for proper chip operation
|
||||
#endif
|
||||
|
||||
/* Set accurate flash wait states */
|
||||
#if (defined(CY_CFG_PWR_ENABLED) && defined(CY_CFG_SYSCLK_CLKHF0_ENABLED))
|
||||
Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0,
|
||||
CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* Function Name: Cy_SystemInit
|
||||
*
|
||||
* \brief This function is called by the start-up code for the selected device.
|
||||
* It performs all of the necessary device configuration based on the design
|
||||
* settings. This includes settings for the platform resources and peripheral
|
||||
* clock.
|
||||
*
|
||||
*/
|
||||
void Cy_SystemInit(void)
|
||||
{
|
||||
/* Configure platform resources */
|
||||
init_cycfg_platform();
|
||||
|
||||
/* Configure peripheral clocks */
|
||||
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0u, 0u);
|
||||
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0u);
|
||||
}
|
||||
|
||||
static int init_cycfg_platform_wraper(struct device *arg)
|
||||
{
|
||||
ARG_UNUSED(arg);
|
||||
SystemInit();
|
||||
return 0;
|
||||
}
|
||||
|
||||
SYS_INIT(init_cycfg_platform_wraper, PRE_KERNEL_1, 0);
|
||||
28
soc/arm/cypress/psoc6/soc.h
Normal file
28
soc/arm/cypress/psoc6/soc.h
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
/*
|
||||
* Copyright (c) 2018, Cypress
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Board configuration macros
|
||||
*
|
||||
* This header file is used to specify and describe board-level aspects
|
||||
*/
|
||||
|
||||
#ifndef _SOC__H_
|
||||
#define _SOC__H_
|
||||
|
||||
#ifndef _ASMLANGUAGE
|
||||
#include <cy_device_headers.h>
|
||||
|
||||
/* ARM CMSIS definitions must be included before kernel_includes.h.
|
||||
* Therefore, it is essential to include kernel_includes.h after including
|
||||
* core SOC-specific headers.
|
||||
*/
|
||||
#include <kernel_includes.h>
|
||||
|
||||
#endif /* !_ASMLANGUAGE */
|
||||
|
||||
#endif /* _SOC__H_ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue