drivers: clock_control: Add STM32G4X clock support
Add clock support for STM32G4X SoC series. Signed-off-by: Richard Osterloh <richard.osterloh@gmail.com>
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b87878d09c
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ca7cbb5a08
8 changed files with 158 additions and 9 deletions
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@ -28,5 +28,6 @@ else()
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L1X clock_stm32l0_l1.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L4X clock_stm32l4_wb.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32WBX clock_stm32l4_wb.c)
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32G4X clock_stm32g4.c)
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endif()
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endif()
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@ -126,6 +126,7 @@ source "drivers/clock_control/Kconfig.stm32h7"
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source "drivers/clock_control/Kconfig.stm32l0_l1"
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source "drivers/clock_control/Kconfig.stm32l4_wb"
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source "drivers/clock_control/Kconfig.stm32g0"
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source "drivers/clock_control/Kconfig.stm32g4"
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# Bus clocks configuration options
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56
drivers/clock_control/Kconfig.stm32g4
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56
drivers/clock_control/Kconfig.stm32g4
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@ -0,0 +1,56 @@
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# Kconfig - STM32G4 PLL configuration options
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#
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# Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_SERIES_STM32G4X
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config CLOCK_STM32_PLL_M_DIVISOR
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int "PLL divisor"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 4
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range 1 16
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help
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PLL divisor, allowed values: 1-16.
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config CLOCK_STM32_PLL_N_MULTIPLIER
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int "PLL multiplier"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 75
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range 8 127
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help
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PLL multiplier, allowed values: 8-127.
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config CLOCK_STM32_PLL_P_DIVISOR
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int "PLL P Divisor"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 7
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range 7 17
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help
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PLL P Output divisor, allowed values: 7, 17.
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config CLOCK_STM32_PLL_Q_DIVISOR
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int "PLL Q Divisor"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 2
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range 2 8
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help
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PLL Q Output divisor, allowed values: 2, 4, 6, 8.
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config CLOCK_STM32_PLL_R_DIVISOR
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int "PLL R Divisor"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 2
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range 2 8
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help
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PLL R Output divisor, allowed values: 2, 4, 6, 8.
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config CLOCK_STM32_LSE
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bool "Low-speed external clock"
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help
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Enable the low-speed external (LSE) clock supplied with a 32.768 kHz
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crystal resonator oscillator.
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endif # SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX
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@ -91,22 +91,26 @@ static inline int stm32_clock_control_on(struct device *dev,
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defined(CONFIG_SOC_SERIES_STM32F4X) || \
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defined(CONFIG_SOC_SERIES_STM32F7X) || \
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defined(CONFIG_SOC_SERIES_STM32F2X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX)
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defined(CONFIG_SOC_SERIES_STM32WBX) || \
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defined(CONFIG_SOC_SERIES_STM32G4X)
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case STM32_CLOCK_BUS_AHB2:
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LL_AHB2_GRP1_EnableClock(pclken->enr);
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break;
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#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F4X ||
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CONFIG_SOC_SERIES_STM32F7X */
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CONFIG_SOC_SERIES_STM32F7X || CONFIG_SOC_SERIES_STM32F2X ||
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CONFIG_SOC_SERIES_STM32WBX || CONFIG_SOC_SERIES_STM32G4X */
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case STM32_CLOCK_BUS_APB1:
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LL_APB1_GRP1_EnableClock(pclken->enr);
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break;
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX)
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defined(CONFIG_SOC_SERIES_STM32WBX) || \
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defined(CONFIG_SOC_SERIES_STM32G4X)
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case STM32_CLOCK_BUS_APB1_2:
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LL_APB1_GRP2_EnableClock(pclken->enr);
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break;
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#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X */
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#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X ||
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CONFIG_SOC_SERIES_STM32WBX || CONFIG_SOC_SERIES_STM32G4X */
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#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
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case STM32_CLOCK_BUS_APB2:
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LL_APB2_GRP1_EnableClock(pclken->enr);
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@ -139,22 +143,25 @@ static inline int stm32_clock_control_off(struct device *dev,
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32F4X) || \
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defined(CONFIG_SOC_SERIES_STM32F7X) || \
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defined(CONFIG_SOC_SERIES_STM32F2X)
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defined(CONFIG_SOC_SERIES_STM32F2X) || \
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defined(CONFIG_SOC_SERIES_STM32G4X)
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case STM32_CLOCK_BUS_AHB2:
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LL_AHB2_GRP1_DisableClock(pclken->enr);
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break;
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#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F4X ||
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CONFIG_SOC_SERIES_STM32F7X */
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CONFIG_SOC_SERIES_STM32F7X || CONFIG_SOC_SERIES_STM32G4X */
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case STM32_CLOCK_BUS_APB1:
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LL_APB1_GRP1_DisableClock(pclken->enr);
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break;
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX)
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defined(CONFIG_SOC_SERIES_STM32WBX) || \
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defined(CONFIG_SOC_SERIES_STM32G4X)
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case STM32_CLOCK_BUS_APB1_2:
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LL_APB1_GRP2_DisableClock(pclken->enr);
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break;
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#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X */
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#endif /* CONFIG_SOC_SERIES_STM32L4X || CONFIG_SOC_SERIES_STM32F0X ||
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CONFIG_SOC_SERIES_STM32WBX || CONFIG_SOC_SERIES_STM32G4X */
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#if !defined (CONFIG_SOC_SERIES_STM32F0X) && !defined (CONFIG_SOC_SERIES_STM32G0X)
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case STM32_CLOCK_BUS_APB2:
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LL_APB2_GRP1_DisableClock(pclken->enr);
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@ -205,7 +212,8 @@ static int stm32_clock_control_get_subsys_rate(struct device *clock,
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case STM32_CLOCK_BUS_APB1:
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#if defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX)
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defined(CONFIG_SOC_SERIES_STM32WBX) || \
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defined(CONFIG_SOC_SERIES_STM32G4X)
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case STM32_CLOCK_BUS_APB1_2:
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#endif
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*rate = apb1_clock;
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68
drivers/clock_control/clock_stm32g4.c
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68
drivers/clock_control/clock_stm32g4.c
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@ -0,0 +1,68 @@
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/*
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* Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <drivers/clock_control.h>
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#include <sys/util.h>
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#include <clock_control/stm32_clock_control.h>
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#include "clock_stm32_ll_common.h"
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#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
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/* Macros to fill up division factors values */
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#define z_pllm(v) LL_RCC_PLLM_DIV_ ## v
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#define pllm(v) z_pllm(v)
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#define z_pllr(v) LL_RCC_PLLR_DIV_ ## v
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#define pllr(v) z_pllr(v)
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/**
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* @brief fill in pll configuration structure
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*/
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void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
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{
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pllinit->PLLM = pllm(CONFIG_CLOCK_STM32_PLL_M_DIVISOR);
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pllinit->PLLN = CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER;
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pllinit->PLLR = pllr(CONFIG_CLOCK_STM32_PLL_R_DIVISOR);
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}
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#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */
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/**
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* @brief Activate default clocks
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*/
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void config_enable_default_clocks(void)
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{
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#ifdef CONFIG_CLOCK_STM32_LSE
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/* LSE belongs to the back-up domain, enable access.*/
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/* Enable the power interface clock */
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
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/* Set the DBP bit in the Power control register 1 (PWR_CR1) */
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LL_PWR_EnableBkUpAccess();
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while (!LL_PWR_IsEnabledBkUpAccess()) {
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/* Wait for Backup domain access */
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}
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/* Enable LSE Oscillator (32.768 kHz) */
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LL_RCC_LSE_Enable();
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while (!LL_RCC_LSE_IsReady()) {
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/* Wait for LSE ready */
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}
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LL_PWR_DisableBkUpAccess();
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#endif
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}
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/**
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* @brief Function kept for driver genericity
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*/
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void LL_RCC_MSI_Disable(void)
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{
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/* Do nothing */
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}
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@ -6,6 +6,7 @@
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#include <arm/armv7-m.dtsi>
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#include <dt-bindings/clock/stm32_clock.h>
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/ {
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cpus {
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};
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soc {
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rcc: rcc@40021000 {
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compatible = "st,stm32-rcc";
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#clock-cells = <2>;
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reg = <0x40021000 0x400>;
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label = "STM32_CLK_RCC";
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};
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};
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@ -12,5 +12,6 @@ config SOC_SERIES_STM32G4X
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select SOC_FAMILY_STM32
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select HAS_STM32CUBE
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select CPU_HAS_ARM_MPU
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select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL
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help
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Enable support for STM32G4 MCU series
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@ -27,6 +27,13 @@
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/* Add include for DTS generated information */
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#include <generated_dts_board.h>
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#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
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#include <stm32g4xx_ll_utils.h>
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#include <stm32g4xx_ll_bus.h>
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#include <stm32g4xx_ll_rcc.h>
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#include <stm32g4xx_ll_system.h>
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#include <stm32g4xx_ll_pwr.h>
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#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
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#endif /* !_ASMLANGUAGE */
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#endif /* _STM32G4_SOC_H_ */
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