cc2650: Add GPIO driver.
Signed-off-by: Geoffrey Le Gourriérec <geoffrey.legourrierec@smile.fr>
This commit is contained in:
Geoffrey Le Gourriérec
Anas Nashif
parent
0abeba8b1a
commit
0a89e00080
5 changed files with 404 additions and 0 deletions
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@ -61,4 +61,6 @@ source "drivers/gpio/Kconfig.pulpino"
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source "drivers/gpio/Kconfig.fe310"
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source "drivers/gpio/Kconfig.cc2650"
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endif # GPIO
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26
drivers/gpio/Kconfig.cc2650
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26
drivers/gpio/Kconfig.cc2650
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@ -0,0 +1,26 @@
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# SPDX-License-Identifier: Apache-2.0
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#
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# GPIO configuration options for the CC2650 SoC (Texas Instruments).
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menuconfig GPIO_CC2650
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bool "TI CC2650 GPIO driver"
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depends on GPIO && SOC_SERIES_CC2650
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default n
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help
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Enable the GPIO driver on boards equipped with TI CC2650.
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if GPIO_CC2650
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# A single block of GPIO exist.
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config GPIO_CC2650_NAME
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string
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default "GPIO_0"
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prompt "GPIO driver name."
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config GPIO_CC2650_INIT_PRIO
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int
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default 40
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prompt "GPIO driver initialization priority."
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endif # GPIO_CC2650
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@ -14,3 +14,4 @@ obj-$(CONFIG_GPIO_CMSDK_AHB) += gpio_cmsdk_ahb.o
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obj-$(CONFIG_GPIO_CC32XX) += gpio_cc32xx.o
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obj-$(CONFIG_GPIO_PULPINO) += gpio_pulpino.o
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obj-$(CONFIG_GPIO_FE310) += gpio_fe310.o
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obj-$(CONFIG_GPIO_CC2650) += gpio_cc2650.o
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348
drivers/gpio/gpio_cc2650.c
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348
drivers/gpio/gpio_cc2650.c
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@ -0,0 +1,348 @@
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/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* GPIO driver for the CC2650 SOC from Texas Instruments.
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*/
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#include <toolchain/gcc.h>
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#include <device.h>
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#include <gpio.h>
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#include <init.h>
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#include <soc.h>
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#include <sys_io.h>
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#include "gpio_utils.h"
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struct gpio_cc2650_data {
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u32_t pin_callback_enables;
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sys_slist_t callbacks;
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};
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/* Pre-declarations */
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static int gpio_cc2650_init(struct device *dev);
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static int gpio_cc2650_config(struct device *port, int access_op,
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u32_t pin, int flags);
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static int gpio_cc2650_write(struct device *port, int access_op,
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u32_t pin, u32_t value);
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static int gpio_cc2650_read(struct device *port, int access_op,
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u32_t pin, u32_t *value);
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static int gpio_cc2650_manage_callback(struct device *port,
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struct gpio_callback *callback,
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bool set);
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static int gpio_cc2650_enable_callback(struct device *port,
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int access_op,
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u32_t pin);
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static int gpio_cc2650_disable_callback(struct device *port,
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int access_op,
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u32_t pin);
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static u32_t gpio_cc2650_get_pending_int(struct device *dev);
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/* GPIO registers */
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static const u32_t doutset31_0 =
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REG_ADDR(TI_CC2650_GPIO_40022000_BASE_ADDRESS,
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CC2650_GPIO_DOUTSET31_0);
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static const u32_t doutclr31_0 =
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REG_ADDR(TI_CC2650_GPIO_40022000_BASE_ADDRESS,
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CC2650_GPIO_DOUTCLR31_0);
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static const u32_t din31_0 =
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REG_ADDR(TI_CC2650_GPIO_40022000_BASE_ADDRESS,
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CC2650_GPIO_DIN31_0);
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static const u32_t doe31_0 =
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REG_ADDR(TI_CC2650_GPIO_40022000_BASE_ADDRESS,
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CC2650_GPIO_DOE31_0);
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static const u32_t evflags31_0 =
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REG_ADDR(TI_CC2650_GPIO_40022000_BASE_ADDRESS,
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CC2650_GPIO_EVFLAGS31_0);
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static struct gpio_cc2650_data gpio_cc2650_data = {
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.pin_callback_enables = 0
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};
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static const struct gpio_driver_api gpio_cc2650_funcs = {
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.config = gpio_cc2650_config,
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.write = gpio_cc2650_write,
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.read = gpio_cc2650_read,
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.manage_callback = gpio_cc2650_manage_callback,
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.enable_callback = gpio_cc2650_enable_callback,
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.disable_callback = gpio_cc2650_disable_callback,
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.get_pending_int = gpio_cc2650_get_pending_int
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};
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DEVICE_AND_API_INIT(gpio_cc2650_0, CONFIG_GPIO_CC2650_NAME,
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gpio_cc2650_init, &gpio_cc2650_data, NULL,
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PRE_KERNEL_1, CONFIG_GPIO_CC2650_INIT_PRIO,
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&gpio_cc2650_funcs);
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static void disconnect(const int pin, u32_t *gpiodoe31_0,
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u32_t *iocfg)
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{
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*gpiodoe31_0 &= ~BIT(pin);
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*iocfg &= ~(CC2650_IOC_IOCFGX_PULL_CTL_MASK |
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CC2650_IOC_IOCFGX_IE_MASK);
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*iocfg |= CC2650_IOC_INPUT_DISABLED |
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CC2650_IOC_NO_PULL;
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}
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/* Configure a single pin.
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* If any asked option is not implementable, rollback entirely to
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* previous configuration.
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*
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* Note: For pin drive strength, the CC2650 devices only support
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* symmetric sink/source capabilities.
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* Thus, you may ONLY determine the common drive strength with
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* GPIO *low output state* flags. Flags for *high output state*
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* will be ignored.
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*/
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static int gpio_cc2650_config_pin(int pin, int flags)
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{
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const u32_t iocfg = REG_ADDR(TI_CC2650_PINMUX_40081000_BASE_ADDRESS,
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CC2650_IOC_IOCFG0 + 0x4 * pin);
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u32_t iocfg_config = sys_read32(iocfg);
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u32_t gpio_doe31_0_config = sys_read32(doe31_0);
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/* Reset all configurable fields to 0 */
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iocfg_config &= ~(CC2650_IOC_IOCFGX_IOSTR_MASK |
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CC2650_IOC_IOCFGX_PULL_CTL_MASK |
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CC2650_IOC_IOCFGX_EDGE_DET_MASK |
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CC2650_IOC_IOCFGX_EDGE_IRQ_EN_MASK |
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CC2650_IOC_IOCFGX_IOMODE_MASK |
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CC2650_IOC_IOCFGX_IE_MASK |
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CC2650_IOC_IOCFGX_HYST_EN_MASK);
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if (flags & GPIO_PIN_DISABLE) {
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disconnect(pin, &gpio_doe31_0_config, &iocfg_config);
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goto commit_config;
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}
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if (flags & GPIO_DIR_OUT) {
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gpio_doe31_0_config |= BIT(pin);
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iocfg_config |= CC2650_IOC_INPUT_DISABLED;
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} else {
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gpio_doe31_0_config &= ~BIT(pin);
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iocfg_config |= CC2650_IOC_INPUT_ENABLED;
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}
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if (flags & GPIO_INT) {
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if (!(flags & GPIO_INT_EDGE) &&
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!(flags & GPIO_INT_DOUBLE_EDGE)) {
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/* Can't do level-based interrupt */
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/* Don't commit changes */
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return -ENOTSUP;
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}
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iocfg_config |= BIT(CC2650_IOC_IOCFGX_EDGE_IRQ_EN_POS);
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if (flags & GPIO_INT_EDGE) {
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if (flags & GPIO_INT_ACTIVE_HIGH) {
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iocfg_config |= CC2650_IOC_POS_EDGE_DET;
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} else {
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iocfg_config |= CC2650_IOC_NEG_EDGE_DET;
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}
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} else if (flags & GPIO_INT_DOUBLE_EDGE) {
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iocfg_config |= CC2650_IOC_NEG_AND_POS_EDGE_DET;
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}
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if (flags & GPIO_INT_CLOCK_SYNC) {
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/* Don't commit changes */
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return -ENOTSUP;
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}
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if (flags & GPIO_INT_DEBOUNCE) {
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iocfg_config |= CC2650_IOC_HYSTERESIS_ENABLED;
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} else {
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iocfg_config |= CC2650_IOC_HYSTERESIS_DISABLED;
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}
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}
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if (flags & GPIO_POL_INV) {
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iocfg_config |= CC2650_IOC_INVERTED_IO;
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} else {
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iocfg_config |= CC2650_IOC_NORMAL_IO;
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}
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if (flags & GPIO_PUD_NORMAL) {
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iocfg_config |= CC2650_IOC_NO_PULL;
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} else if (flags & GPIO_PUD_PULL_UP) {
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iocfg_config |= CC2650_IOC_PULL_UP;
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} else if (flags & GPIO_PUD_PULL_DOWN) {
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iocfg_config |= CC2650_IOC_PULL_DOWN;
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}
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/* Remember, we only look at GPIO_DS_*_LOW ! */
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if (flags & GPIO_DS_DISCONNECT_LOW) {
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disconnect(pin, &gpio_doe31_0_config, &iocfg_config);
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}
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if (flags & GPIO_DS_DFLT_LOW) {
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iocfg_config |= CC2650_IOC_MIN_DRIVE_STRENGTH;
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} else {
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iocfg_config |= CC2650_IOC_MAX_DRIVE_STRENGTH;
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}
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/* Commit changes */
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commit_config:
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sys_write32(iocfg_config, iocfg);
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sys_write32(gpio_doe31_0_config, doe31_0);
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return 0;
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}
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static inline void gpio_cc2650_write_pin(int pin, u32_t value)
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{
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value ? sys_write32(BIT(pin), doutset31_0) :
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sys_write32(BIT(pin), doutclr31_0);
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}
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static inline void gpio_cc2650_read_pin(int pin, u32_t *value)
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{
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*value = sys_read32(din31_0) & BIT(pin);
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}
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static void gpio_cc2650_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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struct gpio_cc2650_data *data = dev->driver_data;
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const u32_t events = sys_read32(evflags31_0);
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const u32_t call_mask = events & data->pin_callback_enables;
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/* Clear GPIO trigger events */
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u32_t evflags = sys_read32(evflags31_0);
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sys_write32(evflags | call_mask, evflags31_0);
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_gpio_fire_callbacks(&data->callbacks, dev, call_mask);
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}
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static int gpio_cc2650_init(struct device *dev)
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{
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ARG_UNUSED(dev);
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/* ISR setup */
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IRQ_CONNECT(TI_CC2650_GPIO_40022000_IRQ_0,
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TI_CC2650_GPIO_40022000_IRQ_0_PRIORITY,
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gpio_cc2650_isr, DEVICE_GET(gpio_cc2650_0),
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0);
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irq_enable(TI_CC2650_GPIO_40022000_IRQ_0);
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return 0;
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}
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static int gpio_cc2650_config(struct device *port, int access_op,
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u32_t pin, int flags)
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{
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ARG_UNUSED(port);
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if (access_op == GPIO_ACCESS_BY_PIN) {
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return gpio_cc2650_config_pin(pin, flags);
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}
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const u32_t nb_pins = 32;
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for (u8_t i = 0; i < nb_pins; ++i) {
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if (pin & 0x1 &&
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gpio_cc2650_config_pin(i, flags) == -ENOTSUP) {
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/* The flags being treated the same for
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* every pin, if we get here then it's
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* necessarily the first pin on which we act.
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*
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* We expect gpio_cc2650_config_pin() to
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* NOT commit its changes if any problem
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* arises, thus we do nothing special here
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* to implement rollback to previous
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* configuration.
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*/
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return -ENOTSUP;
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}
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pin >>= 1;
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}
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return 0;
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}
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static int gpio_cc2650_write(struct device *port, int access_op,
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u32_t pin, u32_t value)
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{
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ARG_UNUSED(port);
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if (access_op == GPIO_ACCESS_BY_PIN) {
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gpio_cc2650_write_pin(pin, value);
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} else {
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const u32_t nb_pins = 32;
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for (u32_t i = 0; i < nb_pins; ++i) {
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if (pin & 0x1) {
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gpio_cc2650_write_pin(i, value);
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}
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pin >>= 1;
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}
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}
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return 0;
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}
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static int gpio_cc2650_read(struct device *port, int access_op,
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u32_t pin, u32_t *value)
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{
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ARG_UNUSED(port);
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if (access_op == GPIO_ACCESS_BY_PIN) {
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gpio_cc2650_read_pin(pin, value);
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*value >>= pin;
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} else {
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const u32_t nb_pins = 32;
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for (u32_t i = 0; i < nb_pins; ++i) {
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if (pin & 0x1) {
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gpio_cc2650_read_pin(i, value);
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}
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pin >>= 1;
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}
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}
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return 0;
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}
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static int gpio_cc2650_manage_callback(struct device *port,
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struct gpio_callback *callback,
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bool set)
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{
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struct gpio_cc2650_data *data = port->driver_data;
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_gpio_manage_callback(&data->callbacks, callback, set);
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return 0;
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}
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static int gpio_cc2650_enable_callback(struct device *port,
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int access_op,
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u32_t pin)
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{
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struct gpio_cc2650_data *data = port->driver_data;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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data->pin_callback_enables |= BIT(pin);
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} else {
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data->pin_callback_enables |= pin;
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}
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return 0;
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}
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static int gpio_cc2650_disable_callback(struct device *port,
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int access_op,
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u32_t pin)
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{
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struct gpio_cc2650_data *data = port->driver_data;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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data->pin_callback_enables &= ~BIT(pin);
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} else {
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data->pin_callback_enables &= ~pin;
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}
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return 0;
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}
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static u32_t gpio_cc2650_get_pending_int(struct device *dev)
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{
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ARG_UNUSED(dev);
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return sys_read32(evflags31_0);
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}
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27
dts/arm/yaml/ti,cc2650-gpio.yaml
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27
dts/arm/yaml/ti,cc2650-gpio.yaml
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@ -0,0 +1,27 @@
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---
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# SPDX-License-Identifier: Apache-2.0
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title: TI CC2650 GPIO
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version: 0.1
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description: >
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This is a representation of the TI CC2650 GPIO node
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properties:
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- compatible:
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type: string
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category: required
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description: compatible strings
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constraint: "ti,cc2650-gpio"
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- reg:
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type: int
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description: mmio register space
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generation: define
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category: required
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- interrupts:
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type: compound
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category: required
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description: required interrupts
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generation: define
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...
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