stm32f4: Add STM32F412 Nucleo board

Add necessary board files, pinmux and device tree in order to have a
usable debug console.

Origin: Original

Change-Id: I43a9d278c3f2c936a714263626722f630367b663
Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>

boards/arm/nucleo_f412zg/Kconfig.board

@@ -0,0 +1,10 @@
+# Kconfig - NUCLEO-144 F412ZG board configuration
+#
+# Copyright (c) 2017 Florian Vaussard, HEIG-VD
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config BOARD_NUCLEO_F412ZG
+	bool "NUCLEO-144 F412ZG Development Board"
+	depends on SOC_STM32F412ZG

boards/arm/nucleo_f412zg/Kconfig.defconfig

@@ -0,0 +1,13 @@
+# Kconfig - NUCLEO-144 F412ZG board configuration
+#
+# Copyright (c) 2017 Florian Vaussard, HEIG-VD
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if BOARD_NUCLEO_F412ZG
+
+config BOARD
+	default nucleo_f412zg
+
+endif # BOARD_NUCLEO_F412ZG

boards/arm/nucleo_f412zg/Makefile

@@ -0,0 +1,2 @@
+# No C files (yet)
+obj- += dummy.o

boards/arm/nucleo_f412zg/board.h

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2017 Florian Vaussard, HEIG-VD
+ *
+ * Based on nucleo_f411re:
+ *
+ * Copyright (c) 2016 Matthias Boesl
+ * Copyright (c) 2017 Linaro Limited.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INC_BOARD_H
+#define __INC_BOARD_H
+
+#include <soc.h>
+
+/* USER push button */
+#define USER_PB_GPIO_PORT	"GPIOC"
+#define USER_PB_GPIO_PIN	13
+
+/* LD1 green LED */
+#define LD1_GPIO_PORT		"GPIOB"
+#define LD1_GPIO_PIN		0
+
+/* LD2 blue LED */
+#define LD2_GPIO_PORT		"GPIOB"
+#define LD2_GPIO_PIN		7
+
+/* LD3 red LED */
+#define LD3_GPIO_PORT		"GPIOB"
+#define LD3_GPIO_PIN		14
+
+/* Create aliases to make the basic samples work */
+#define SW0_GPIO_NAME		USER_PB_GPIO_PORT
+#define SW0_GPIO_PIN		USER_PB_GPIO_PIN
+#define LED0_GPIO_PORT		LD1_GPIO_PORT
+#define LED0_GPIO_PIN		LD1_GPIO_PIN
+#define LED1_GPIO_PORT		LD2_GPIO_PORT
+#define LED1_GPIO_PIN		LD2_GPIO_PIN
+#define LED2_GPIO_PORT		LD3_GPIO_PORT
+#define LED2_GPIO_PIN		LD3_GPIO_PIN
+
+#endif /* __INC_BOARD_H */

boards/arm/nucleo_f412zg/doc/nucleo412zg.rst

@@ -0,0 +1,165 @@
+.. _nucleo_f412zg_board:
+
+ST Nucleo F412ZG
+################
+
+Overview
+********
+
+The Nucleo F412ZG board features an ARM Cortex-M4 based STM32F412ZG MCU
+with a wide range of connectivity support and configurations. Here are
+some highlights of the Nucleo F412ZG board:
+
+
+- STM32 microcontroller in LQFP144 package
+- Two types of extension resources:
+       - ST Zio connector including: support for Arduino™ Uno V3 connectivity
+         (A0 to A5, D0 to D15) and additional signals exposing a wide range of
+         peripherals
+       - ST morpho extension pin headers for full access to all STM32 I/Os
+- On-board ST-LINK/V2-1 debugger/programmer with SWD connector
+- Flexible board power supply:
+       - 5 V from ST-LINK/V2-1 USB VBUS
+       - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho
+         connectors, 5 V on ST morpho connector
+- Three user LEDs
+- Two push-buttons: USER and RESET
+
+.. image:: img/Nucleo144_perf_logo_1024.png
+     :width: 720px
+     :align: center
+     :height: 720px
+     :alt: Nucleo F412ZG
+
+More information about the board can be found at the `Nucleo F412ZG website`_.
+
+Hardware
+********
+
+Nucleo F412ZG provides the following hardware components:
+
+- STM32F412ZGT6 in LQFP144 package
+- ARM®32-bit Cortex®-M4 CPU with FPU
+- 100 MHz max CPU frequency
+- VDD from 1.7 V to 3.6 V
+- 1 MB Flash
+- 256 KB SRAM
+- GPIO with external interrupt capability
+- 12-bit ADC with 16 channels, with FIFO and burst support
+- RTC
+- 14 General purpose timers
+- 2 watchdog timers (independent and window)
+- SysTick timer
+- USART/UART (4)
+- I2C (4)
+- SPI (5)
+- SDIO
+- USB 2.0 OTG FS
+- DMA Controller
+- CRC calculation unit
+
+More information about STM32F412ZG can be found here:
+       - `STM32F412ZG on www.st.com`_
+       - `STM32F412 reference manual`_
+
+Supported Features
+==================
+
+The Zephyr nucleo_412zg board configuration supports the following hardware features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port-polling;                |
+|           |            | serial port-interrupt               |
++-----------+------------+-------------------------------------+
+| PINMUX    | on-chip    | pinmux                              |
++-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | gpio                                |
++-----------+------------+-------------------------------------+
+| PWM       | on-chip    | pwm                                 |
++-----------+------------+-------------------------------------+
+
+Other hardware features are not yet supported on this Zephyr port.
+
+The default configuration can be found in the defconfig file:
+
+	``boards/arm/nucleo_f412zg/nucleo_f412zg_defconfig``
+
+
+Connections and IOs
+===================
+
+Nucleo F412ZG Board has 8 GPIO controllers. These controllers are responsible for pin muxing,
+input/output, pull-up, etc.
+
+Available pins:
+---------------
+.. image:: img/nucleo_f412zg_zio_left.png
+     :width: 720px
+     :align: center
+     :height: 540px
+     :alt: Nucleo F412ZG ZIO connectors (left)
+.. image:: img/nucleo_f412zg_zio_right.png
+     :width: 720px
+     :align: center
+     :height: 540px
+     :alt: Nucleo F412ZG ZIO connectors (right)
+.. image:: img/nucleo_f412zg_morpho_left.png
+     :width: 720px
+     :align: center
+     :height: 540px
+     :alt: Nucleo F412ZG Morpho connectors (left)
+.. image:: img/nucleo_f412zg_morpho_right.png
+     :width: 720px
+     :align: center
+     :height: 540px
+     :alt: Nucleo F412ZG Morpho connectors (right)
+
+For more details please refer to `STM32 Nucleo-144 board User Manual`_.
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+- UART_3_TX : PD8
+- UART_3_RX : PD9
+- PWM_2_CH1 : PA0
+- USER_PB : PC13
+- LD1 : PB0
+- LD2 : PB7
+- LD3 : PB14
+
+System Clock
+------------
+
+Nucleo F412ZG System Clock could be driven by internal or external oscillator,
+as well as main PLL clock. By default System clock is driven by PLL clock at 96MHz,
+driven by 8MHz high speed external clock.
+
+Serial Port
+-----------
+
+Nucleo F412ZG board has 4 UARTs. The Zephyr console output is assigned to UART3.
+Default settings are 115200 8N1.
+
+
+Programming and Debugging
+*************************
+
+Nucleo F412ZG board includes an ST-LINK/V2-1 embedded debug tool interface.
+However this interface is currently not supported by openocd. You will need
+to use ST tools or an external JTAG probe.
+
+
+.. _Nucleo F412ZG website:
+   http://www.st.com/en/evaluation-tools/nucleo-f412zg.html
+
+.. _STM32 Nucleo-144 board User Manual:
+   http://www.st.com/resource/en/user_manual/dm00244518.pdf
+
+.. _STM32F412ZG on www.st.com:
+   http://www.st.com/en/microcontrollers/stm32f412zg.html
+
+.. _STM32F412 reference manual:
+   http://www.st.com/resource/en/reference_manual/dm00180369.pdf

boards/arm/nucleo_f412zg/nucleo_f412zg_defconfig

@@ -0,0 +1,41 @@
+CONFIG_ARM=y
+CONFIG_BOARD_NUCLEO_F412ZG=y
+CONFIG_SOC_SERIES_STM32F4X=y
+CONFIG_SOC_STM32F412ZG=y
+# 96MHz system clock (highest value to get a precise USB clock)
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
+
+# Enable MPU
+CONFIG_STM32_ARM_MPU_ENABLE=y
+
+# enable USART3 - passthrough to STLINK v2 connector
+CONFIG_UART_STM32_PORT_3=y
+# enable console on this port by default
+CONFIG_UART_CONSOLE_ON_DEV_NAME="UART_3"
+
+# enable pinmux
+CONFIG_PINMUX=y
+
+# enable GPIO ports A, B, C
+CONFIG_GPIO=y
+
+# clock configuration
+CONFIG_CLOCK_CONTROL=y
+
+# Clock configuration for Cube Clock control driver
+CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
+CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
+# use HSE as PLL input
+CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
+# however, the board does not have an external oscillator, so just use
+# the 8MHz clock signal coming from integrated STLink
+CONFIG_CLOCK_STM32_HSE_BYPASS=y
+# produce 96MHz clock at PLL output
+CONFIG_CLOCK_STM32_PLL_M_DIVISOR=8
+CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=384
+CONFIG_CLOCK_STM32_PLL_P_DIVISOR=4
+CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=8
+CONFIG_CLOCK_STM32_AHB_PRESCALER=1
+CONFIG_CLOCK_STM32_APB1_PRESCALER=2
+CONFIG_CLOCK_STM32_APB2_PRESCALER=1

drivers/pinmux/Makefile

@@ -14,6 +14,7 @@ obj-$(CONFIG_BOARD_NUCLEO_F401RE) += stm32/pinmux_board_nucleo_f401re.o
 obj-$(CONFIG_BOARD_STM32F4_DISCO) += stm32/pinmux_board_stm32f4_disco.o
 obj-$(CONFIG_BOARD_STM32F469I_DISCO) += stm32/pinmux_board_stm32f469i_disco.o
 obj-$(CONFIG_BOARD_NUCLEO_F411RE) += stm32/pinmux_board_nucleo_f411re.o
+obj-$(CONFIG_BOARD_NUCLEO_F412ZG) += stm32/pinmux_board_nucleo_f412zg.o
 obj-$(CONFIG_BOARD_NUCLEO_F413ZH) += stm32/pinmux_board_nucleo_f413zh.o
 obj-$(CONFIG_BOARD_96B_CARBON) += stm32/pinmux_board_carbon.o
 obj-$(CONFIG_BOARD_NUCLEO_L476RG) += stm32/pinmux_board_nucleo_l476rg.o

drivers/pinmux/stm32/pinmux_board_nucleo_f412zg.c

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2017 Florian Vaussard, HEIG-VD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <kernel.h>
+#include <device.h>
+#include <init.h>
+#include <pinmux.h>
+#include <sys_io.h>
+#include "pinmux/pinmux.h"
+
+#include "pinmux_stm32.h"
+
+/* pin assignments for NUCLEO-F412ZG board */
+static const struct pin_config pinconf[] = {
+#ifdef CONFIG_UART_STM32_PORT_3
+	{STM32_PIN_PD8, STM32F4_PINMUX_FUNC_PD8_USART3_TX},
+	{STM32_PIN_PD9, STM32F4_PINMUX_FUNC_PD9_USART3_RX},
+#endif /* #ifdef CONFIG_UART_STM32_PORT_3 */
+#ifdef CONFIG_PWM_STM32_2
+	{STM32_PIN_PA0, STM32F4_PINMUX_FUNC_PA0_PWM2_CH1},
+#endif /* CONFIG_PWM_STM32_2 */
+};
+
+static int pinmux_stm32_init(struct device *port)
+{
+	ARG_UNUSED(port);
+
+	stm32_setup_pins(pinconf, ARRAY_SIZE(pinconf));
+
+	return 0;
+}
+
+SYS_INIT(pinmux_stm32_init, PRE_KERNEL_1,
+		CONFIG_PINMUX_STM32_DEVICE_INITIALIZATION_PRIORITY);

dts/arm/Makefile

@@ -16,6 +16,7 @@ dtb-$(CONFIG_BOARD_96B_CARBON)		=	96b_carbon.dts_compiled
 dtb-$(CONFIG_BOARD_96B_CARBON_NRF51)	=	96b_carbon_nrf51.dts_compiled
 dtb-$(CONFIG_BOARD_NUCLEO_F401RE)	=	nucleo_f401re.dts_compiled
 dtb-$(CONFIG_BOARD_NUCLEO_F411RE)	=	nucleo_f411re.dts_compiled
+dtb-$(CONFIG_BOARD_NUCLEO_F412ZG)	=	nucleo_f412zg.dts_compiled
 dtb-$(CONFIG_BOARD_NUCLEO_F413ZH)	=	nucleo_f413zh.dts_compiled
 dtb-$(CONFIG_BOARD_NUCLEO_F103RB)	=	nucleo_f103rb.dts_compiled
 dtb-$(CONFIG_BOARD_STM3210C_EVAL)	=	stm3210c_eval.dts_compiled

dts/arm/nucleo_f412zg.dts

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2017 Florian Vaussard, HEIG-VD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/stm32f412.dtsi>
+
+/ {
+	model = "STMicroelectronics STM32F412ZG-NUCLEO board";
+	compatible = "st,stm32f412zg-nucleo", "st,stm32f412";
+
+	chosen {
+		zephyr,console = &usart3;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+};
+
+&usart3 {
+	current-speed = <115200>;
+	status = "ok";
+};

dts/arm/nucleo_f412zg.fixup

@@ -0,0 +1,14 @@
+/* This file is a temporary workaround for mapping of the generated information
+ * to the current driver definitions.  This will be removed when the drivers
+ * are modified to handle the generated information, or the mapping of
+ * generated data matches the driver definitions.
+ */
+
+
+#define CONFIG_NUM_IRQ_PRIO_BITS	ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
+
+#define CONFIG_UART_STM32_PORT_3_BASE_ADDRESS	ST_STM32_USART_40004800_BASE_ADDRESS
+#define CONFIG_UART_STM32_PORT_3_BAUD_RATE	ST_STM32_USART_40004800_CURRENT_SPEED
+#define CONFIG_UART_STM32_PORT_3_IRQ_PRI	ST_STM32_USART_40004800_IRQ_0_PRIORITY
+#define CONFIG_UART_STM32_PORT_3_NAME		ST_STM32_USART_40004800_LABEL
+#define PORT_3_IRQ				ST_STM32_USART_40004800_IRQ_0

scripts/sanity_chk/arches/arm.ini

@@ -9,7 +9,7 @@ platforms = qemu_cortex_m3 frdm_k64f arduino_due nucleo_f103rb stm32_mini_a15
             sam_e70_xplained curie_ble nrf52_blenano2 hexiwear_kw40z
             cc3220sf_launchxl frdm_kl25z disco_l475_iot1 nucleo_l432kc
             nucleo_f413zh stm32l496g_disco stm32f4_disco 96b_carbon_nrf51
-            stm32f469i_disco
+            stm32f469i_disco nucleo_f412zg
 
 supported_toolchains = zephyr gccarmemb