A lot of the entry.S is again implemented in common/vector.S.
I removed everything redundant and changed the jump to the common
symbol __start at the end.
Signed-off-by: Greter Raffael <rgreter@baumer.com>
.bss and .data are uncached in Zephyr builds for intel_adsp. No need
to try to manipulate cache of objects in those sections.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Instead of custom SOC_MCAUSE_EXP_MASK definition. Note that SoCs
selecting RISCV_PRIVILEGED already used such config indirectly (see
changes in soc_common.h).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The MCAUSE register has the "Interrupt" flag defined defined at XLEN-1
position (31 for 32-bit, 63 for 64-bit). This is not an SoC specific
option, and there's no need to expose it publicly.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
As defined in Table 3.6 of "The RISC-V Instruction Set Manual, Volume
II: Privileged Architecture". Delete all spread definitions of the same,
weirdly prefixed with "SOC".
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
SOC_ESP32_NET is now SOC_ESP32_APPCPU, following espressif's
naming convention in the same manner as ESP32S3 app cpu.
SOC_ESP32_APPCU is now a subset of SOC_SERIES_ESP32.
This commit also changes the necessary files, samples and tests
for bisect purposes.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Commit 447a492 switched to `sys_cache*` to enable caches at SoC init. To
preserve the old behavior of enabling caches at init, is missing to
select `CONFIG_CACHE_MANAGEMENT`.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Because it was exclusively used by the "common" RISC-V privileged code
to build CPU idle routines that are now handled by arch level code.
Also, all platforms defaulted to "y", making it pointless in practice.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Since d992683db5 (soc: arm: replace redundant config option for
caches for nxp_imx), RT1xxx series will not have cache enabled at boot
unless CONFIG_CACHE_MANAGEMENT=y. Since this will improve performance,
enable CONFIG_CACHE_MANAGEMENT by default.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This patch enhances the power-down sequence for the HOST (HST) domain
within the Intel ADSP ACE 1.5 architecture. It introduces a check to
ensure that a specific condition, represented by a magic key value, is
met before disabling the HST domain. This additional verification step
ensures that the HST domain is only powered down when it is safe to do
so, thereby maintaining the stability and reliability of the system.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch introduces power management for the HOST (HST) domain within
the Intel ADSP ACE IP. It adds macros to access the node identifier and
device pointer for the HST power domain and integrates power management
calls into the system initialization and power state transition
functions.
The patch ensures that power gating of the HST domain is prevented when
the primary core of the audio DSP is active. Preventing power gating is
crucial for maintaining the functionality of the HST domain while the
primary DSP core is performing critical tasks.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Gigadevice was inconsistent with the convention established by other SoC
families, that is, use <vnd_prefix>_<family>. For example, ST STM32 uses
st_stm32. Note that GD32VF103, under soc/riscv, has already been
adjusted.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Use sys_cache* functions to enable the caches for stm32f7 and
stm32h7. This ensures that CONFIG_CACHE_MANAGEMENT is
considered correctly.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Use the sys_cache* functions to enable the caches on same70 and
samv71. This will ensure that CONFIG_CACHE_MANAGEMENT is
considered correctly.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Remove the redundant cache config options for kv5x and use
the sys_cache* functions to enable the caches. This will automatically
consider CONFIG_CACHE_MANAGEMENT.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Replace the redundant cache config options for the nxp_imx and
use sys_cache* functions to enable the caches. These will automatically
consider CONFIG_CACHE_MANAGEMENT.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Use sys_cache* for enabling the caches in nxp_s32. This automatically
considers CONFIG_CACHE_MANAGEMENT and will activate the
cases only if this is active.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
This option is no longer needed, all SoCs have been moved out from
soc/riscv/riscv-privileged folder.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Reorganized as follows:
- Created a new SiFive Freedom family
- Created 3 new series: E300/E500/E700
- Created Socs within each series (e.g. E340)
Also moved out of riscv-privileged folder.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Merge both series into a new family: microchip_miv [1], moving them out
of riscv-privileged. Updated naming to stay closer to what vendor
announces on their website.
[1]: https://www.microchip.com/en-us/products/fpgas-and-plds/
fpga-and-soc-design-tools/mi-v
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Move out of riscv-privileged and convert to a standalone SoC. Note
that the family/series structure has been dropped in favor of a single
SoC (what NEORV32 seems to be).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Move things out from riscv-privileged, and create the new RISC-V GD32
family. New family folder follows the <vnd>_<family> naming convention.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Reorganize following the hierarchy found in the vendor website [1]:
- SoC Family: Telink TLSR
- SoC series: TLSR951X
- SoC: TLSR9518
Also split out from riscv-privileged folder. Note that B91 was the name
of a starter kit [2].
[1]: http://wiki.telink-semi.cn/wiki/chip-series/TLSR951x-Series/
[2]: https://wiki.telink-semi.cn/wiki/Hardware/
B91_Generic_Starter_Kit_Hardware_Guide/
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
So that SoCs can be ported outside of riscv-privileged folder, setting
their own family name. This will be removed once all SoCs are ported.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Introduce a new arch level Kconfig option to signal the implementation
of the RISCV Privileged ISA spec. This replaces
SOC_FAMILY_RISCV_PRIVILEGED, because this is not a SoC specific
property, nor a SoC family.
Note that the SoC family naming scheme will be fixed in upcoming
commits.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The header is common to all Nuclei based cores (not strictly related to
RISCV privileged spec). Since only GD32VF103 uses a Nuclei core, move
the file to its SoC folder.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add a new riscv/common directory where to store common code between
SoCs, e.g. those implementing the privileged spec.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
S32K1xx devices have a maximum of 3 FlexCAN peripherals. Each part may
define a different maximum number of instances and message buffers,
hence the interrupt lines are defined in the part specific dts.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Adds common thread-local-storage.ld provided
by Zephyr. This also fixes a wrong xtensa_core entry
that should be riscv_core.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
When Power Management is enabled (CONFIG_PM=y),
the CONFIG_IDLE_STACK_SIZE of 320 is not enough :
Increase its size to 512.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
The defconfig.series file for the stm32f4 incorrectly redefines
the PM Kconfig in order to select two dependencies, COUNTER and
COUNTER_RTC_STM32_SUBSECONDS, instead of setting a default for
them if PM is included.
This commit fixes the error described above.
Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
Added GPIOTE0, GPIOTE1 instances for legacy devices,
GPIOTE20, GPIOTE30 for Moonlight and GPIOTE130,
GPIOTE131 instances for Haltium.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Currently SOF has disabled CONFIG_PM_DEVICE_RUNTIME_EXCLUSIVE option and
use pm_suspend_devices() to suspend and resume IPC device during D3
power flow. The pm_suspend_devices() function skips suspending devices
that are busy. In very rare cases, the IPC device is busy during the
power state transition, which results in the device not being restored
during reboot. This happens when FW sends a message to the HOST and
waits for ACK, and the HOST simultaneously sends a SET_DX message to the
DSP. This suspend/resume logic in IPC driver does not work well when the
system enters the D3 state because it is not a suspend state, but rather
a power-off. IPC does not require suspending, only reinitialization when
exiting D3. We cannot avoid this one missing ACK and it cannot block the
DSP from turning off.
When FW receives a SET_DX message it checks whether it can enter the D3
state and then returns an error (via IPC) or calls the pm_state_force
function. Success response is sent directly from power_down assembly and
not via ipc driver. This is because after receiving the response, the
HOST will turn off the DSP.
In order for the transition to D3 to take place, only the primary core
can be active, all pipes must be stopped (and therefore all modules in
FW). The only active thread at this time is the Idle thread. Driver on
the host will not send another ipc because is still waiting for
response. FW can try to send only two notification:
- FW exception: from this place there is no return to continue the power
transition,
- log buffer status: skipped, they remain in the queue without being
sent.
I'm moving pm_device_busy_clear(dev) from IRQ handler to
intel_adsp_ipc_send_message function so the pending ACK does not block
power transition.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Give option in soc.c to initialize the MIPI DPHY clock from the default
AUX1_PLL, or from the FRO using CONFIG_MIPI_DPHY_CLK_SRC_FRO.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
HDA DMA driver uses an excessive value of 128 bytes as required alignment
for DMA buffer size. This may result in the correct buffer size (e.g.
32-byte aligned, which is DT-compliant) being silently truncated before
writing it into DGBS register. This patch changes the requirement to the
value implied by DGBS register format (effectively reduces to 16 bytes).
Signed-off-by: Tomasz Lissowski <tomasz.lissowski@intel.com>
The previous implementation of the sys_arch_reboot function
for the Atmel SAM series was using NVIC_SystemReset.
This caused a reboot time of around 20 seconds on a SAM4SA16CA,
which is now reduced by directly writing to the
reset controller control register (RSTC_CR).
Signed-off-by: Jaro Van Landschoot <jaro.vanlandschoot@basalte.be>
Co-authored-by: Gerson Fernando Budke <nandojve@gmail.com>
Adopt the "MMU_REGION_DT_FLAT_ENTRY" macro to automatically generate
elements in "mmu_regions" according to devicetree "compatible" and
"status".
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
Adopt the "MMU_REGION_DT_FLAT_ENTRY" macro to automatically generate
elements in "mmu_regions" according to devicetree "compatible" and
"status".
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
QEMU MMU tracing showed that there might be something wrong with
its Xtensa MMU implementation, which result in access violation
when running samples/userspace/hello_world_user.
Here is the MMU trace from QEMU from failed runs:
get_pte: autorefill(00109020): PTE va = 20000424, pa = 0010c424
get_physical_addr_mmu: autorefill(00109020): 00109000 -> 00109006
xtensa_cpu_tlb_fill(00109020, 1, 0) -> 00109020, ret = 0
xtensa_cpu_tlb_fill(00109028, 1, 0) -> 00109028, ret = 0
xtensa_cpu_tlb_fill(00109014, 0, 2) -> 00103050, ret = 26
The place where it fails is during reading from 0x109014.
From the trace above, the auto-refill maps 0x109000 correctly
with ring 0 and RW access with WB cache (which should be correct
the first time under kernel mode). The page 0x109000 is the libc
partition which needs to be accessible from user thread.
However, when accessing that page, the returned physical address
became 0x103050 (and resulting in load/store access violation).
We always identity map memory pages so it should never return
a different physical address.
After forcing TLB invalidation during page table swaps, the MMU
trace is:
get_pte: autorefill(00109020): PTE va = 20000424, pa = 0010c424
get_physical_addr_mmu: autorefill(00109020): 00109000 -> 00109006
xtensa_cpu_tlb_fill(00109020, 1, 0) -> 00109020, ret = 0
get_pte: autorefill(00109028): PTE va = 21000424, pa = 0010e424
get_physical_addr_mmu: autorefill(00109028): 00109000 -> 00109022
xtensa_cpu_tlb_fill(00109028, 1, 0) -> 00109028, ret = 0
get_pte: autorefill(00109014): PTE va = 21000424, pa = 0010e424
get_physical_addr_mmu: autorefill(00109014): 00109000 -> 00109022
xtensa_cpu_tlb_fill(00109014, 0, 2) -> 00109014, ret = 0
xtensa_cpu_tlb_fill(00109020, 0, 0) -> 00109020, ret = 0
Here, when the same page is accessed, it got the correct PTE
entry, which is ring 2 with RW access mode (but no cache).
Actually accessing the variable via virtual address returns
the correct physical address: 0x109014.
So workaround that by forcing TLB invalidation during page swap.
Fixes#66029
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
There is no need for this config here and it is messing
with total sys heap calculation.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Add SOC definition for MK22F12 series, larger LQFP-144 K22 series
parts that feature additional peripheral instances.
Additionally, these parts differ from the standard MK22 in the following
ways:
- SYSMPU peripheral is present, so an MPU definition is required
- No external oscillator divider is present
This commit also updates the NXP HAL to include pin control files for
these SOCs.
Signed-off-by: Daniel DeGrasse <daniel@degrasse.com>
Supporting Stop1 mode while BLE RF is enabled requires some specific
adaptation and usage of STM32WBA Cube BLE controller scm API.
scm (Secure clock manager) is in charge of switching clock depending
on RF status and should be informed of PM stop modes scheduling.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
STM32WBA controller uses a PKA driver to perform cyphering operations
on keys. Since PKA hardware block requires RNG clock to be enabled, a
synchronization with zephyr RNG driver is needed.
Use RNG enable status to check if RNG could be switched off or needs to
be switched on.
Similarly in entropy driver, don't cut RNG clock if PKA is enabled.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Kconfig options with a HEAP_MEM_POOL_ADD_SIZE_ prefix should be used to
set the minimum required system heap size. This helps prevent
applications from creating a non-working image by trying to set a too
small value.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
Kconfig options with a HEAP_MEM_POOL_ADD_SIZE_ prefix should be used to
set the minimum required system heap size. This helps prevent
applications from creating a non-working image by trying to set a too
small value.
Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
In order to enable BLE support on STM32WBA, following APIs are implemented:
- HostStack_: BLE Controller scheduling
- ll_sys_: Link layer API required for scheduling
- UTIL_TIMER_: BLE Controller timer utility
- LINKLAYER_PLAT_: BLE controller utilities
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
The DC233C core has support for both i-cache and d-cache.
So mark it as such so we can test caching of Xtensa in QEMU.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Definition of ADSP_FORCE_DECOUPLED_HDMA_L1_EXIT_BIT,
which is used in the intel_adsp_force_dmi_l0_state function,
is missing.
Signed-off-by: Fabiola Kwasowiec <fabiola.kwasowiec@intel.com>
Currently on zephyr, RAIL library is used only by Bluetooth applications,
with this update, it will be able to be used for sample applications
for custom radio phys.
All files were copied from Silicon Labs GSDK v4.2.4.
Signed-off-by: Zoltan Havas <zoltan.havas@silabs.com>
The STM32F722 is similar to the STM32F723, but lacks the latter's
more advanced USB PHY. Otherwise, they are virtually identical.
Signed-off-by: Evan Perry Grove <evan@4grove.com>
Separating two new functions force and allow l1
to have the current state with separated functions
in the ipc file so that SOF can call these
functions via IPC DMI_FORCE_L1_EXIT. Change related
to the addition of a new parameter to force
DMI L1 exit on IPC request.
Signed-off-by: Fabiola Kwasowiec <fabiola.kwasowiec@intel.com>
This gets rid of the z_ prefix.
Note that z_xt_*() are being used by the HAL so they cannot be
renamed.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This follows the idea to remove any z_ prefix. Since MMU has
a large number of these, separate out these changes into one
commit to ease review effort.
Since these are no longer have z_, these need proper doxygen
doc. So add them too.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Header files under arch/xtensa/include are considered internal
to architecture. There is really no need for two places to
house architecture internal header files.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Simply to provide some consistencies on file naming under
arch/xtensa.
These are all internally used files and are not public.
So there is no need to provide a deprecation path for
them.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch enables DSP clock gating for ACE platforms. By default, clock
gating is blocked by the firmware in the hardware configuration. If
CONFIG_ADSP_IDLE_CLOCK_GATING is enabled, this prevent is not active and
clock can be gated when core is in idle state. WIth this option disabled
clock gating will only be enabled in hardware during power gating.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
The STM32 G4 series has a built-in Arm Instrumentation Trace
Macrocell. Set CONFIG_HAS_SWO to enable this.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Configure the SYS_CLOCK_TICKS_PER_SEC directly from the
DTS st-prescaler property of the lptim node
aka stm32_lp_tick_source
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The instruction cache in the STM32F7 and H7 was enabled regardless
of the value assigned via Kconfig to the CONFIG_ICACHE parameter.
This commit adds the missing conditional checks; note that this does
not affect the compiled behavior unless CONFIG_ICACHE is explicitly
disabled by the user.
Remove a redundant low-level check on DCache being already enabled,
since it is also performed inside the SCB_EnableDCache function.
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
Use the already available in the tree mechanism of adding assembly
instructions right after WFI/WFE to implement the workaround for
nRF5340 anomaly 168 (replace the 4 NOP solution used on the network
core as it turned out to be insufficient) and provide two related
Kconfig options so that users are able to adjust the workaround to
their actual needs (disable it entirely or use it in the extended
version).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This patch adds definitions for the nRF9151,
which is software-compatible with nRF9161.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Enable the TF-M NS storage partition for nordic boards.
This partition is otherwise not used, and configured as secure.
Fixes: #59376
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Currently Code Cache cannot be enabled because its initialization is
guarded by Kconfig options which depend on CPU core cache support,
but S32K14x devices has a SoC specific L1 cache controller. Hence,
introduce a SoC-specific symbol to enable Code Cache.
Note that the cache controller is not available for S32K11x devices.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Update the Kconfig for the npcx eSPI driver so it's automatically
enabled if the devicetree node is enabled.
Signed-off-by: Keith Short <keithshort@google.com>
Microchip's PolarFire SoC (MPFS) has 186 available interrupts.
Fix the Kconfig symbols.
While we're at at: remove commented out code
Signed-off-by: Conor Paxton <conor.paxton@microchip.com>
GCLK Gen 2 was dedicated to USB, but never setup... this patch
configures it for 48 MHz, derrived from DFLL.
Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
Following changes in #64978, align CPU_HAS_xCACHE symbols with
the CMSIS feature definitions in the device headers so that
both have the same value.
Fixes#66147
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Some SoC have missing feature selections in their Kconfig.
Some others are missing includes of CMSIS-Core headers.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Caches are optional on cortex-m7, having CPU_HAS_*CACHE in CPU_CORTEX_M7
definition renders them mandatory.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
This changes remove extraneous includes causing issues with cycles in
includes subsequently having code requiring definitions from CMSIS
while it’s configuration hasn’t completed yet.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Kconfig parameters, header’s default & silicon vendor’s SDK configuration
for CMSIS Core, must be consistent. Depending on the inclusion order of
the headers, this is currently not always the case.
This change introduces consistency checks & enusers defaults match their
Kconfig settings.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Introduce support for NXP S32K1 family of 32-bit MCUs, and
particularly for S32K146 devices. S32K1 share a fair amount of
similarities with Kinetis family, so most of the peripheral drivers
can be reused.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit is a part of introduction of new WTD instances.
It adds new Kconfig symbols that can be used in WDT shim and
nrfx driver.
Signed-off-by: Adam Wojasinski <adam.wojasinski@nordicsemi.no>
In an earlier commit, the riscv-privileged level implementation of
`arch_cpu_idle()` is not included unless `CONFIG_RISCV_HAS_CPU_IDLE` is
enabled.
This commit ensures the option is enabled on all the existing CPUs, thereby
maintaining the existing behavior.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
The current configuration comes with a common implementation of
`arch_cpu_idle()` for the whole riscv-privileged family, utilizing the
`WFI` instruction to place the CPU into a light sleep state, with the
assumption that it will be awakened later by interrupts such as SYSTICK.
However, this approach is not always effective, particularly in scenarios
where the SYSTICK is not a valid wake source.
This commit uses `CONFIG_RISCV_HAS_CPU_IDLE` as the build condition of the
family-level `idle.c`, allowing CPUs that do not enable this option to
fallback to a generic arch-level implementation in
`arch/riscv/core/cpu_idle.c`.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
Change makes EGU instance used for anomaly 109 workaround configurable.
The default EGU instance (5) may be used for other purpose.
Signed-off-by: Marek Pieta <Marek.Pieta@nordicsemi.no>
Reset cause reason was not initalized properly, making
hwinfo feature not to work as expected.
Fixes#65634
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
There are symbols are both defined by the NXP S32 HAL and
the CMSIS RTOS V2 wrapper, to avoid interference between
them, redefine the symbols under an enum.
Also this is may a common issue for all NXP S32 platforms,
move to common place to be reused
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
introduce global DSP_SHARING and CPU_HAS_DSP to be used by all
architectures and change existing usage in ARC to use those global
configs.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
r8a779f0 SoC is part of the Renesas R-Car Gen4 SoC series.
This SoC has a dual core lockstep Cortex-R52 CPU.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Renesas R-Car Gen4 is different from Gen3 regarding pinmux.
While Gen3 had only one base address to manage all pins,
Gen4 has one set of pinmux registers per GPIO banks.
We could expose one pinmux register per GPIO controllers,
but that would break potential compatibility with Linux
Device tree.
Instead create a reg_base array to parse all reg base from
device tree and identify proper base address based on the pin
definition.
This imply to add a pfc_base parameter to most of the pfc_rcar
function.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Signed-off-by: Pierre Marzin <pierre.marzin@iot.bzh>
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
The original SHI module only has one output FIFO buffer. It costs a lot
when the driver has to send/change the protocol control code because it
must fill out all 128 bytes of output FIFO. In npcx4, we introduce
another output buffer in 1-byte depth. These two buffers can switch back
and forth during the transaction. We can use the single-byte buffer
to send the control code and the 128-byte FIFO to send the data payload.
It helps improve the SHI driver's efficiency.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Secondary dsp is idle and waiting for interrupt before it is totally
halted. The other active cores can trigger idc interrupt to this core,
this can wake it up and result to fw panic. Mask idc interrupt as timer
interrupt to prevent this case.
Signed-off-by: Rander Wang <rander.wang@intel.com>
Annotate posix_exit() and nsi_exit() as noreturn
mainly to ease the life of static analysis tools.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Andy Ross re-implementation of MMU layer with some subtle changes,
like re-using existent macros, fix page table cache property when
direct mapping it in TLB.
From Andy's original commit message:
This is a reworked MMU layer, sitting cleanly below the page table
handling in the OS. Notable differences from the original work:
+ Significantly smaller code and simpler API (just three functions to
be called from the OS/userspace/ptable layer).
+ Big README-MMU document containing my learnings over the process, so
hopefully fewer people need to go through this in the future.
+ No TLB flushing needed. Clean separation of ASIDs, just requires
that the upper levels match the ASID to the L1 page table page
consistently.
+ Vector mapping is done with a 4k page and not a 4M page, leading to
much more flexibility with hardware memory layout. The original
scheme required that the 4M region containing vecbase be mapped
virtually to a location other than the hardware address, which makes
confusing linkage with call0 and difficult initialization
constraints where the exception vectors run at different addresses
before and after MMU setup (effectively forcing them to be PIC
code).
+ More provably correct initialization, all MMU changes happen in a
single asm block with no memory accesses which would generate a
refill.
Signed-off-by: Andy Ross <andyross@google.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Add soc power management for the STM32F4x chips.
One low power state is added supported by all chips from the family -
the Stop mode with voltage regulator in low-power mode.
The Stop mode for STM32F chips has to work with the IDLE timer -
CORTEX_M_SYSTICK_IDLE_TIMER, because PLL and HSI are disabled in the
Stop mode (Systick is not clocked). The only possible wakeup source is
RTC, which works as a IDLE timer for the Systick.
The exit latency may need to be adjusted per system, depending on the
system tick frequency and other variables.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
This commit moves configuration of hfxo from headers defined on board level
to device trees of SoCs.
Signed-off-by: Franciszek Zdobylak <fzdobylak@antmicro.com>
Some workarounds were introduced for intel cavs2.5 platform bring up.
It is not general so move them to platform code.
Signed-off-by: Rander Wang <rander.wang@intel.com>
Cavs platforms starts from Apllolake to Raptorlake. Some of them need some
workaround for arch_cpu_idle so create a bespoken one. Each workaround is
configured by kconfig setting.
Signed-off-by: Rander Wang <rander.wang@intel.com>
The xtensa/nxp_adsp_imx8m linker script is missing
the necessary include statements for linker snippets.
So we need to add them.
This fixes compile warnings like: orphan section `.unstable_id'
from `modules/chre/lib..__modules__lib__chre__platform__zephyr.a
(version.cc.obj)' being placed in section `.unstable_id'.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Add _heap_sentry value to fix build errors for
newlib, like: "undefined reference to `_heap_sentry'"
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
When linking, in crtbegin.o for C++ exception support, we pull in
the .tm_clone_table section.
Update the linker scripts to handle this, otherwise we get a
"warning: orphan section `.tm_clone_table'".
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Remove platform.h since is no longer used for SOF.
Move memory.h to include folder and modify the linker
to reflect this.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
The SoC header already includes the necessary device headers for
all SoC variants supported.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
To simplify the inclusion of device headers in common code for
NXP S32 devices, make sure all SoCs are including their respective
device headers. This PR adds the missing headers for S32Z/E.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Add alias "FEATURE_SIUL2_MAX_NUMBER_OF_INPUT"
for compatibility with with previous RTD versions.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Currently, the NXP S32 SoCs have three redundant Kconfig hidden
options to define the part number. To streamline this, we will
retain `CONFIG_SOC_PART_NUMBER` to store the part number as a
string and `CONFIG_SOC_PART_NUMBER_<part>` that can be selected
by the boards.
Furthermore, for drivers requiring conditional code compilation
based on the target SoC, they should utilize the series or SoC
config option as applicable, instead of the part number config.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The existing S32K3 Kconfig options employ the `M7` suffix, which is
redundant given that all cores in this series utilize an Arm Cortex-M7
core. Therefore, we should remove it.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
To accommodate support for S32K1 devices, it is necessary to rename
the existing `s32k` directory, which currently houses support for
the S32K3 series, to align with the respective series names. This
adjustment is necessary given the distinct differences in core
architecture, MPU, peripherals, and other key aspects between
the two series.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
CPU_HAS_NRF_IDAU is depending on SOC_SERIES_NRF91X and
SOC_NRF5340_CPUAPP.
This makes it more difficult to have an out-of-tree nrf SOC.
It is also an unnecessary dependency. There is no prompt for
CPU_HAS_NRF_IDAU, so it will not show up in menuconfig and it won't be
possible to enable it from a users Kconfig fragment.
The only way to enable it is to select it, and those that select this
option can themselves make sure that they only do so when appropriate.
Also, move NRF_SPU options out to SOC Kconfig files to also make
out-of-tree SoCs possible. With the added benefit of not polluting the
common soc/arm/Kconfig.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
This adds a new driver for Renesas RZ/T2M.
The driver allows configuration of pin direction,
pull up/down resistors, drive strength and slew rate,
and selection of function for a pin.
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
This adds a new SoC: SOC_RENESAS_RZT2M
and a new board: rzt2m_startek_kit
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
Co-authored-by: Roman Dobrodii <rdobrodii@antmicro.com>
This allows XIP to be disabled for applications that execute in
RAM, which do not need XIP support from flash
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Add support for mipi_dsi_detach API to dsi_mcux_2l driver, and
update RT5xx SOC interface to enable halting clocks for the MIPI DPHY.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
i.MX93 share similiar register layout with i.MX RT11xx. Change ccm driver
to align with i.MX RT11xx, and make it easier to enable other drivers.
Signed-off-by: Chekhov Ma <chekhov.ma@nxp.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Enable NXP FlexRAM in DTS and SOC code.
Do not configure flexram at runtime if the code is in the RAM.
Fix RT1060 DT to be more accurate.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Other drivers like the pinctrl_ti_k3 rely on a fully initialized system.
Move the am62x_init to an earlier stage than PRE_KERNEL_1 to keep both
PRE_KERNEL_{1,2} free for drivers.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
- Make caparray delta a Kconfig variable
- Set caparray delta for beagle_bcf at beagleconnect_freedom_defconfig
Signed-off-by: Ayush Singh <ayushdevel1325@gmail.com>
Signed-off-by: Jason Kridner <jkridner@beagleboard.org>
Support NXP MRT on LPC55XXX SOC series, enable on
lpcxpresso55s69_cpu0, add test overlay to counter basic api test
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
As the name suggests, this commit attempts to cleanup some
of the configurations for the i.MX8 series. This cleanup
consists of either relocating the configuration or removing
unnecessary configurations.
As a rule of thumb, SoC-specific configurations have been moved
to Kconfig.series. If the configuration is by default 'y' and
needs to be set to 'n' or it has a numeric value then it has
been moved to Kconfig.defconfig.series. Configurations that
are default 'n' and were also explicitly set to 'n' have been
removed. Also, enabling logging has been moved to the board
level to avoid having to force all boards based on the same
SoC to enable logging.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit attempts to clean the memory.h header by doing
the following changes:
1) Change the include guard to the standard
ZEPHYR_....
2) Remove unused macro definitions.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Since platform.h is a SOF-specific header that's no
longer used there's no point in keeping the include/soc directory.
As such, move memory.h to include/ and modify the linker script
to reflect this location change.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This commit attempts to split the generic i.MX8 SoC into its
QXP and QM variants. As things are now, the i.MX8 SoC doesn't
have any NXP HAL files to back it up. As a consequence, the
native Zephyr drivers cannot be used.
To solve this issue, the generic i.MX8 has been split into
i.MX8QXP and i.MX8QM, each of them having different NXP HAL
files.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Most of the public APIs in `riscv_plic.h`
(except `riscv_plic_get_irq` & `riscv_plic_get_dev`) expect the
`irq` argument to be in Zephyr-encoded format, instead of the
previously `irq_from_level_2`-stripped version. The first level
IRQ is needed by `intc_plic` to differentiate between the
parent interrupt controllers, so that correct ISR offset can be
obtained using the LUT in `sw_isr_common`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
NXP USB bindings were combined into one binding and using
a property corresponding to HAL enums which is improper use
of devicetree.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
This CL is to minimize `CONFIG_SOC_SERIES_XXXX` definitions when we
introduce a new chip series. Most of them are relevant to register
layouts in different npcx soc series. It moves soc-specific register
definitions from `reg_def.h` to its own soc.h file.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Add a property for I2C channel switch selection. This property will
write to the SMBxxCHS register according to the I2C node you selected,
which can make channel swapping.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics and defining the driver's ISR within the shim
driver itself.
Note that for some peripheral instances is needed to redefine the
HAL macros of the peripheral base address, since the naming is not
uniform for all instances.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Fix cmake depreciation warning on pre-defined linker.id
(soc/arm/renesas_ra/ra4m1/linker.ld) used for arduino_uno_r4_minima.
Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
Allow user to disable CONFIG_ADJUST_DCDC for their board, rather than
selecting it at the SOC level. The symbol still defaults to enabled,
preserving existing behavior unless a user explicitly chooses to disable
it.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
At present, many of the NXP S32 shim drivers do not make use of
devicetree instance-based macros because the NXP S32 HAL relies on an
index-based approach, requiring knowledge of the peripheral instance
index during both compilation and runtime, and this index might not
align with the devicetree instance index.
The proposed solution in this patch eliminates this limitation by
determining the peripheral instance index during compilation
through macrobatics.
Note that for some peripheral instances is needed to define the
HAL macros of the peripheral base address because there are gaps
in the instances or there are SoCs with a single instance.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Several paths are checked for existence before added as global Zephyr
include path.
The existence check was needed because some tooling emit warnings on
non-existing paths.
Only few SoCs are using those pre-defined paths, yet this code runs
for all SoCs. The principle originates back from Kbuild days, and with
CMake it's more common and generally more visible to let the CMake code
defining libraries to specify include paths.
Furthermore it appears that several SoC implementation following the
<soc-path>/include was unaware that the path would be automatically
added as include path, cause they contain lines like:
zephyr_library_include_directories(include)
Remove pre-defineds path except the `<SOC_PATH>` path, which is
guaranteed to exists.
This simplifies the CMake logic in the top-level Zephyr CMakeLists.txt
file.
This cleanup further prepares for future work where SoCs need not to
be organised under architectures which is important for multi-arch SoCs.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit introduce 'USE_SWITCH' feature into cortex-A/R(aarch32)
architecture
For introducing USE_SWITCH, the exception entry and exit are unified via
`z_arm_cortex_ar_enter_exc` and `z_arm_cortex_ar_exit_exc`. All
exceptions including ISR are using this way to enter and exit exception
handler.
Differentiate exception depth and interrupt depth. Allow doing
context switch when exception depth greater than 1 but not allow doing
this when interrupt depth greater than 1.
Currently, USE_SWITCH doesn't support FPU_SHARING and USERSPACE.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
This is support for AArch64 development board.
The board uses 4-core Cortex-A55, which are based on
the ARMv8.2 architecture.
In addition,we support smp support and
it can use 4-cores to run basic samples.
Signed-off-by: Charlie Xiong <1981639884@qq.com>
Commit c6e3bac4f changed the core clock frequency of LPC55XXX series.
That clock is used by the cortex-m systick timer, which is the
default timer used for system time in zephyr on this series.
The bug is that the config SYS_CLOCK_HW_CYCLES_PER_SEC default was not
updated on the affected platforms to account for this change, so system
time is currently recorded as 150% of reality. Fix this by changing the
kconfig to be set automatically at SOC level and remove board defaults.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
For this SoC, an additional section is conditionally included on top of
the default linker script for Cortex-M. Set `SOC_LINKER_SCRIPT` to the
local `linker.ld`.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Remove CONFIG_IPM_IMX_REV2, as this Kconfig is no longer needed. The
driver can now be enabled with CONFIG_IPM_IMX.
Update NXP HAL to remove this Kconfig as well.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Remove nxp,imx-mu-rev2 compatible. This IP block is the same as the
nxp,imx-mu device, and should be handled by the same compatible
Instead, use CONFIG_HAS_MCUX to determine which HAL APIs should be used
to interact with the messaging unit IP.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit updates all x86 SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit updates all xtensa SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit updates all sparc SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit updates all riscv SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit updates all posix SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit updates all mips SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit updates all arm64 SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit updates all arm SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
This commit updates all arc SoCs to set SOC_LINKER_SCRIPT CMake
variable to point to active linker script directly.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Save secondary dsp context when it is powered off in idle thread
and restore it when the secondary dsp is powered up. The algorithm
is aligned with ace platform.
Tested on a tgl platform.
Signed-off-by: Rander Wang <rander.wang@intel.com>
Settings which defaults to `y` but is architecture related should have
a arch dependency for safety reasons.
Thefore add `if SPARC` to the SPARC_CASA Kconfig to ensure this setting
is only enabled on the sparc arch.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Fix a bug on cavs platform that secondary core is not powered off
by SET_DX ipc message sometimes. Secondary core is set into idle
state when switching to SOF_OFF state and then halted by primary
core. The interrupt is enabled before entring idle state, so the
secondary core may be woken up by interrupt and soc_cpus_active
is set to true before it is halted by hardware power gating. This
result to error when SOF check soc_cpus_active after the secondary
is halted.
This patch doesn't enable interrupt before idle entry to avoid above issue.
Signed-off-by: Rander Wang <rander.wang@intel.com>
Locate common mpu code together with other arm / nxp mpu code in the
arch folder where it logically belongs.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
it8xxx2 uses a custom linker script, which was not updated on
dfb3674c4c. This patch naively updates it
to support DEVNULL_REGION.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Mark .noinit section as NOLOAD and move it
next to the other NOLOAD sections. This way
it is removed from a generated image that is
embedded in the rt595 app image.
Signed-off-by: Mike J. Chen <mjchen@google.com>
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
To avoid complicating the initial code for supporting the SoC,
I have implemented only the bare minimum for now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Add initial support for Renesas RA clock generation circuit.
It returns a fixed value to simplify the first commit to get the UART
working now.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
Relocate multi-level interrupts APIs out of `irq.h` into
a new file named `irq_multilevel.h` to provide cleaner
separation between typical irq & multilevel ones.
Added preprocessor versions of `irq_to_level_x` as `IRQ_TO_Lx`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
This adds a if CONFIG_SOC_FAMILY_NXP_ADSP guard in
Kconfig.defconfig for nxp_adsp. Or else all of its default
get applied everywhere. For example, qemu_xtensa fails
kernel.logging.message_capture tests because
CONFIG_TEST_LOGGING_DEFAULTS is disabled in
nxp_adsp/Kconfig.defconfig which should not have applied
to qemu_xtensa at all. So put a guard in there.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
PM should not be enabled by default at the soc level. This is an
application decision and not a platform decision whether to enable or
disable PM features.
Enabling PM by default will result in descripencies and test scope and
failures in tests that do not account for PM being enabled.
Fixes#60359
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Force STM32_ENABLE_DEBUG_SLEEP_STOP option when running tests.
This option enables Debug in Sleep/stop states and disables it when
disabled (default state).
When disabled, it may be impossible to flash the device with runner
such as openocd. It's generally working using cubeprogrammer, but it might
fail as well with fault configuration.
Instead of fixing each test or breaking CI each time a new test is created
with CONFIG_PM=y, force this option to be enabled when ZTEST=y (as it was
already the case when DEBUG=y).
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Cortex-R52 supports both Arm and Thumb-2 mode, but Zephyr's ASM
code for Armv-8 Aarch32 is written for Arm mode only. This Soc
has a general purpose register that can set the core TEINIT signal
to change the mode exceptions are taken before booting up the core.
The debugger startup scripts or firmware booting up the core may
configure this bit to Thumb mode, as is the case of the NXP S32 debug
probe startup scripts for S32ZE.
Due to above reason, clear SCTLR.TE bit at reset so that TEINIT value
is ignored and exceptions are always taken into Arm mode, compatible
with current Zephyr ASM code. At least until taking execeptions in Thumb
mode is supported in Zephyr.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
In preparation for RT500 ADSP enablement, consolidate common Xtensa
configuration parameters in top level Kconfig.defconfig.
Signed-off-by: Dmitry Lukyantsev <dmitrylu@google.com>
ESP32 flash_mmap() function requires `_rodata_reserved_start` address
to be at the beginning of RODATA. This allows adding memory-mapped flash
areas.
Fixes#52764
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This commit adds an implementation of poweroff, which first
uses SUPC to enable all defined wakeup sources (except for
sam4l), followed by entering backup mode.
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
Now the API to manage GPREGRET register is unified for all devices
having one or more GPREGRET entries.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Add generic SoC support for the supported nordic SoCs:
- nrf5340
- nrf9160
- nrf9120
Add generic SoC support by taking board specific configurations from
zephyr devicetree and kconfig.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Let's make the sync_rtc kconfig depend on the SOC_COMPATIBLE
options which are set both by the real and simulated targets,
so this code works in the same way for both.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This patch contains small refactor of lpsram init function (defines
registers and adds new macro).
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
The Kconfig option HAS_PM, which must be needed for SoCs providing PM
hooks, is missing in npcx4.
This commit adds it to soc/arm/nuvoton_npcx/npcx4/Kconfig.series.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This variant uses the same die as IT82202/IT82302 series and has
a pinout compatible with IT513xx series packages.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This changes qemu_xtensa to use dc233c core instead of
sample_controller. The sample_controller uses a very
basic configuration which lacks features usually needed
in real world applications. Instead, use the dc233c core
as the base for qemu_xtensa so we can use QEMU to cover
more of our code path.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commits adds the DA14695 variant.
The main difference with the DA14699 is a smaller package with less
GPIO.
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
If the channel was used for 16bit in the once, subsequent 32bit sample size
audio will be broken since the SCS bit remains set.
Example sequence with SOF:
normal audio playback with 16bit
ChainDMA audio playback with 16bit
normal audio playback with 16bit
The last playback results garbled audio.
Introduce intel_adsp_hda_set_sample_container_size() helper function
to handle the SCS bit and use it in the driver.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
- if we have input enable use CY_GPIO_DM_xxxx else
CY_GPIO_DM_xxx_IN_OFF;
- added bias_high_impedance option
- Updated HIGHZ drive mode, now it sets if:
--- we have bias_high_impedance
--- or if input_enable and no addition bias mode
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Coupling in code between workarounds for anomaly 160 and anomaly 165
(pretick) is decreased.
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
It might happen that while some interrupt handler other than for RTC0
or RTC1 (e.g. for RADIO) is executed, the scheduled pretick CC triggers.
This starts pretick pulses due to the loop through IPC. The change
in pretick schedule did not stop the pretick pulses going through IPC
loop, what caused heavy increase in power consumption.
This commit fixes this behavior.
Added also clarifications for Kconfig option `SOC_NRF53_RTC_PRETICK`.
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
For RTC0 events the RTC1 pretick event was not cleared what caused the
WDT to be not stopped. This resulted in increased power usage.
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
rand32.h does not make much sense, since the random subsystem
provides more APIs than just getting a random 32 bits value.
Rename it to random.h and get consistently with other
subsystems.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Do not clock the LPC55xxx cores from PLL1 when CONFIG_FLASH is set. This
is required due to the following limitation of the flash controller
(documented in the reference manual):
Flash operations (erase, blank check, program) and reading a single word
can only be performed for CPU frequencies of up to 100 MHz. These
operations cannot be performed for frequencies above 100 MHz.
The PLL1 clock source will result in a core clock of 150MHz, which
violates this requirement.
Fixes#62963
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add the ESP32-C3-WROOM-02 modules with 4 or 8 MiB flash. The
temperature and antenna / connector variants are not mentioned
explicitely as they do not influence the software.
Signed-off-by: Detlev Zundel <dzu@member.fsf.org>
Increase the `ndev` of PLIC to the max of 1024 from 53, as
supported by the RISCV PLIC. The total number of IRQs is now
1035(1024 + 11), up from 64(53 + 11).
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Added SOC_GECKO_HAS_RADIO symbol, to indicate that a SoC has a radio
phy, so that radio related code would only apply to devices with radio.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
When build ISH project in Chromium repo, the coverage report error:
zmake build --coverage rex-ish
lcov: ERROR: no valid records found in tracefile.
To fix this, enable coverage config to link ISH boards with coverage
library.
Signed-off-by: Li Feng <li1.feng@intel.com>
Commit 759e07bebe ("intel_adsp: move memory window setup to
PRE_KERNEL_1") moved memory window setup from EARLY to
PRE_KERNEL_1. Similar change must be done to boot_complete, or
otherwise boot-up sequence will not be completed correctly
on all platforms.
Suggested-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The `SOC_NRF53_RTC_PRETICK` option is now allowed to be used with
`NRF_802154_RADIO_DRIVER`.
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
The nrf53 pretick can be used with non-zero
`NRF_RTC_TIMER_USER_CHAN_COUNT` Kconfig option.
The nrf53 pretick requires just one RTC1 CC channel.
The nrf53 pretick handles also RTC1 and RTC0 both CCs and OVERFLOW
events by examination of events scheduled on them. The pretick is set
based on number of ticks to the closest event scheduled that can trigger
an interrupt.
Because the operation in `z_arm_on_enter_cpu_idle` hook would
take too much time with interrupts disabled, the
`z_arm_on_enter_cpu_idle_prepare` hook enabled by Kconfig option
`ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK` is used. It performs RTC0 and RTC1
examination, and sets pretick without interrupts being blocked.
The LDREX/STREX are leveraged to detect if exception took place
between start of `z_arm_on_enter_cpu_idle_prepare` and
`z_arm_on_enter_cpu_idle`. If exception has not been taken, the pretick
calculation can be trusted because source data could not changed and
too much time could not pass. Otherwise the sleep attempt is disallowed,
the idle will loop again and try later.
Prompt for `SOC_NRF53_RTC_PRETICK` Kconfig option allows to control
this option by an user and turn the feature off if necessary.
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
Add RTC pretick option that triggers HW activity one tick before and
RTC event that leads to the interrupt. Option is active only on nrf53
network core.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
As a development helper, add a kconfig option to
automatically start the MCU this Zephyr image is built
for during HW boot, even if in other circumstances
this MCU would not start automatically (for ex. because
another core is meant to release its reset).
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
To be more accurate, as this option represents a microcontroller
number, not a CPU number.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add a new kconfig option to be able to pass extra images to the
native simulator build.
So one can, for ex., use one application build to produce one core image,
and at the same time have it produce the final link with the native
simulator runner and the other MCU images.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This renames the board from qemu_xtensa_dc233c to
qemu_xtensa_mmu to better signal that it is for testing with
MMU on QEMU Xtensa. Also turn on testing by default to make
sure future changes will not break Xtensa MMU support.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
On S32K344, the offset in memory map between each channel
is 0x4000 for most channels, but there is specific case is
between channel 11 and 12 which is 0x1D4000 instead. As a
consequence, 32 channels are divided to two parts: one
starts from channel 0 -> 11. The other is from channel 128
to 145. The channel gap is from 12 -> 127.
For user and data structures in shim driver, the channel's
value comes from 0 --> 31. Above constraint will be counted
when interact with the mcux sdk
Beside that, the DMAMUX register in this platform is very
specific, not in identical with DMAMUX channel, so shim
driver is updated to cover this case
Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
MEC172X has 2 package sizes with additional pins on the -LJ package.
This commit separates the package-specific parts into different files.
In addition, this patch removes unnecessary package-specific enums in
favor of calculated offsets into the desired registers.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
These headers are using things like `uint32_t` & devicetree
macros, so they should include the `devicetree.h` & `types.h`.
Otherwise they depend on the parent file to have those headers
included before they are included.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The old CONFIG_UART_NS16550_ACCESS_IOPORT has been used to
indicate whether to access the NS16550 UART via IO port
before device tree is used to describe hardware. Now we have
device tree, and we can specify whether a particular UART
needs to be accessed via IO port using property io-mapped.
Therefore, CONFIG_UART_NS16550_ACCESS_IOPORT is no longer
needed (and thus also CONFIG_UART_NS16550_SIMULT_ACCESS).
Remove these two kconfigs and modify code to use device tree
to figure out how to access the UART hardware.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The symbol _end is used to indicate the start of heap in
the common libc malloc code. On ACE, heap is in uncached
area. However, _end was in the cached area while end of
heap is in uncached area. This resulted in incorrect
calculation of heap size. So move _end into uncached
area so correct heap size can be calculated.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Select the newly introduced nrf53 compatible kconfig options.
These are common both for real HW and for simulated HW,
allowing SW to behave appropriately for both.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add support for SMARTDMA to RT5xx SOCs. SMARTDMA ram banks will be
powered up, so code can be programmed into this region for the SMARTDMA
engine.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adds CONFIG_STM32_ENABLE_DEBUG_SLEEP_STOP to allow debugger attaching in
sleep/stop mode of STM32 parts. Mainly useful for debugging. Move DBGMCU
from part-sepcific power.c to common soc_config.c. CONFIG_USE_SEGGER_RTT
depends on this as well.
Signed-off-by: Roland Lezuo <roland.lezuo@embedded-solutions.at>
Add node for VREF0 peripheral to LPC55S3X SOC DT
Clock VREF peripheral if status = okay in DT
Enable VREF on lpcxpresso55s36
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Enable clock control driver for NXP S32ZE SoCs and add clock sources
definitions for devicetree.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
PRE_KERNEL_1 is more suited for dealing with devices, so move out of
EARLY.
Verified on hardware and things seem to behave the same. Something was
changed since this was first introduced as this was not possible for
some reason.
Fixes#62627
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The ARM Cryptocell 310/312 IP is wrapped by Nordic specific registers.
It is organized as follows:
- Base address: Nordic wrapper
- Base address + 0x1000: ARM Cryptocell IP registers
Following more standard devicetree conventions, use a single node for
what is exposed as a single peripheral. The node contains 2 register
entries, one for the wrapper and a second one for the 3rd party IP.
Compatibles are used from more specific (nordic,cryptocell) to more
generic (arm,cryptocell-3xx).
Other minor fixes: peripheral is disabled by default (as it should be in
SoC dts files).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Just like for the nrf52_bsim let's add helper kconfig symbols
which can be used to identify we are running in a target that
is compatible with the real HW but is not the real HW.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This commit:
* adds the `CONFIG_SOC_GECKO_SERIES0` Kconfig option for Gecko Series 0
SoCs
* selects the proper `CONFIG_SOC_GECKO_SERIESx` option where it's currently
missing
Fixes#62806.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Flash segments require VMA to proper work. Executing from LMA
is not possible. Current implementation did not take into account
runtime iterable rom sections that any application could implement.
In the above cenario and as reported in the issue below, ESP32 won't run
when those ROM sections are created in application level.
This change make sure all flash segments are properly mapped
accordingly.
Fixes#61834
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Selecting Low Power clock has the same result as selecting High
Performance clock (now IPLL). Therefore, the LP clock will be removed
from the list of available clocks on ACE family platforms.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Updating value of WOVRCO request bit in CLKCTL register according to the
documentation. Previus value was mask used for clock enabling.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
The iMX RT bootrom allows the user to load images into RAM regions from
flash by providing a correctly configured boot header. In particular, if
the boot header contains a load address within RAM, the bootroom will
automatically copy the image to the load address before executing it
Introduce CONFIG_NXP_IMX_RT_ROM_RAMLOADER to enable this feature. This
Kconfig will shift the LMA of a image built to run in a RAM region to
reside in the default FlexSPI boot region, which allows the image to be
loaded to the FlexSPI region using west. This is intended to simplify
development of applications executing from RAM on iMX RT based systems.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add check for device busy when CONFIG_PM_NEED_ALL_DEVICES_IDLE is
set to y because one or more devices may still in busy and causes
problem when system go into low power in Intel ISH platform.
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
This is the final step in making the `zephyr,memory-attr` property
actually useful.
The problem with the current implementation is that `zephyr,memory-attr`
is an enum type, this is making very difficult to use that to actually
describe the memory capabilities. The solution proposed in this PR is to
use the `zephyr,memory-attr` property as an OR-ed bitmask of memory
attributes.
With the change proposed in this PR it is possible in the DeviceTree to
mark the memory regions with a bitmask of attributes by using the
`zephyr,memory-attr` property. This property and the related memory
region can then be retrieved at run-time by leveraging a provided helper
library or the usual DT helpers.
The set of general attributes that can be specified in the property are
defined and explained in
`include/zephyr/dt-bindings/memory-attr/memory-attr.h` (the list can be
extended when needed).
For example, to mark a memory region in the DeviceTree as volatile,
non-cacheable, out-of-order:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_VOLATILE |
DT_MEM_NON_CACHEABLE |
DT_MEM_OOO )>;
};
The `zephyr,memory-attr` property can also be used to set
architecture-specific custom attributes that can be interpreted at run
time. This is leveraged, among other things, to create MPU regions out
of DeviceTree defined memory regions on ARM, for example:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-region = "NOCACHE_REGION";
zephyr,memory-attr = <( DT_ARM_MPU(ATTR_MPU_RAM_NOCACHE) )>;
};
See `include/zephyr/dt-bindings/memory-attr/memory-attr-mpu.h` to see
how an architecture can define its own special memory attributes (in
this case ARM MPU).
The property can also be used to set custom software-specific
attributes. For example we can think of marking a memory region as
available to be used for memory allocation (not yet implemented):
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_NON_CACHEABLE |
DT_MEM_SW_ALLOCATABLE )>;
};
Or maybe we can leverage the property to specify some alignment
requirements for the region:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_CACHEABLE |
DT_MEM_SW_ALIGN(32) )>;
};
The conventional and recommended way to deal and manage with memory
regions marked with attributes is by using the provided `mem-attr`
helper library by enabling `CONFIG_MEM_ATTR` (or by using the usual DT
helpers).
When this option is enabled the list of memory regions and their
attributes are compiled in a user-accessible array and a set of
functions is made available that can be used to query, probe and act on
regions and attributes, see `include/zephyr/mem_mgmt/mem_attr.h`
Note that the `zephyr,memory-attr` property is only a descriptive
property of the capabilities of the associated memory region, but it
does not result in any actual setting for the memory to be set. The
user, code or subsystem willing to use this information to do some work
(for example creating an MPU region out of the property) must use either
the provided `mem-attr` library or the usual DeviceTree helpers to
perform the required work / setting.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Xen-related Kconfig options were highly dependand on BOARD/SOC xenvm.
It is not correct because Xen support may be used on any board and SoC.
So, Kconfig structure was refactored, now CONFIG_XEN is located in
arch/ directory (same as in Linux kernel) and can be selected for
any Cortex-A arm64 setup (no other platforms are currently supported).
Also remove confusion in Domain 0 naming: Domain-0, initial domain,
Dom0, privileged domain etc. Now all options related to Xen Domain 0
will be controlled by CONFIG_XEN_DOM0.
Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
Move memory mapping of Xen node to Grant Table driver system init
function. After moving mapping we don't need anymore records of
xen-xen node into 'mmu_regions' array, so they were deleted from
all SoCs: Rcar Gen3/Gen4 and XenVM.
We need at least 16M of virtual address space to map memory of Xen
node, so the virtual memory sized has been increased to 32 MB, it
should be enough for basic use-cases and mapping of 16M mem region
of Xen node.
Unfortunately, after moving we also need to increase number of XLAT
tables. The previous code was more efficient if we talking about
usage of XLAT tables, because it mapped grant tables using a higher-
order table that allows mapping blocks of 2MB. And after the changes
is maps every 4KB page, so we need more XLAT tables.
Increase number of grant frames, it is needed to sync stage 1 and stage 2
memory mappings, previously we map only one page on stage 2 and further
usage of unmap regions can cause MMU translation errors.
Perform mapping stage 1 before mapping for stage 2 (add to physmap),
because right after stage 1 we can try to access memory and if it is
unmap in stage 2, error will be received during translation.
Note: Xen Grant Table driver doesn't use Zephyr Device Model.
Authored-by: Mykola Kvach <mykola_kvach@epam.com>
Co-authored-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Configure SWO reference frequency to be the same as
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC. This should make all ST boards ready to
be used with SWO, without configuring any other devicetree property.
Tested with NUCLEO-L476RG and NUCLEO-H563ZI.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
This commit follows the parent commit work.
This commit introduces the following major changes.
1. Move all directories and files in 'include/zephyr/arch/arm/aarch32'
to the 'include/zephyr/arch/arm' directory.
2. Change the path string which is influenced by the changement 1.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
It doesn't make sense to keep the aarch32 directory in the
'arch/arm/core' directory as the aarch64 has been moved out.
This commit introduces the following major changes.
1. Move all directories and files in 'arch/arm/core/aarch32' to
'arch/arm/core' and remove the 'arch/arm/core/aarch32' directory.
2. Move all directories and files in 'arch/include/aarch32' to
'arch/include' and remove the 'arch/include/aarch32' directory.
3. Remove the nested including in the 'arch/include/kernel_arch_func.h'
and 'arch/include/offsets_short_arch.h' header files.
4. Change the path string which is influenced by the changement 1
and 2.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
This is a private kernel header with private kernel APIs, it should not
be exposed in the public zephyr include directory.
Once sample remains to be fixed (metairq_dispatch), which currently uses
private APIs from that header, it should not be the case.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Remove `threshold-reg-offset` DT property and implement them with static
inline functions in `reg_def.h`
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add multi-device support in npcx adc driver since there is more than one
adc module in npcx4 series. And each adc's reference voltage might be
different, this CL introduces the `vref-mv` prop. to select its own
reference voltage.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Signed-off-by: Kate Yen <htyen@nuvoton.com>
The 'CCFG' (Customer Configuration) occupies 88 bytes in topmost flash
sector (8 KiB) and is by default always included in the final image.
This disables including CCFG part when building images for chain-loading
by the MCUboot bootloader.
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
Introduce I2C target transfer using the PIO mode. Add an option
"target-pio-mode" in the yaml file, determined by the DTS, to dictate
whether I2C target transfer uses the PIO mode.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Disable the timeout setting when both the clock and data are
in a low state. This allows for I2C host clock stretching
without a timeout limit.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Added devicetree and Kconfig for EFR32MG12P433F1024GM68, needed for
the BRD4170A radio board by Silicon Labs.
Signed-off-by: Warren Buffer <warren.buffer78@gmail.com>
Created set of new functions for configure fir coefficients with support
for packed format. This allowed to make the dai_dmic_set_config_nhlt
function simpler.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
All fir filters have an identical set of registers so their definitions
were combined to simplify the code. From the dai_dmic_set_config_nhlt
function, a duplicate piece of code responsible for configuring fir was
separated into a new function.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
All PDM controllers have the same set of registers. Their definitions have
been merged to simplify the code.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Add a new kconfig option to select which embedded
CPU we are targetting.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The assert on L3_MEM_BASE_ADDR is incorrect, we need must convert
to uncached before use.
Fixes: ffd2121c65 ("soc: xtensa: intel_adsp: cavs: fix
power_down_cavs() signature")
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
To properly setup L1 exit timing this patch will use buffer interrupt
for HOST DMA and wait for Host HDA to actually start
First interrupt will clear all others.
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Adjust the memory organization to avoid overlapping
critical regions from bootloaders (MCUboot and IDF)
Signed-off-by: Almir Okato <almir.okato@espressif.com>
Since __sha256_ram_block section must in the first 4KB,
h2ram_pool section is no longer included first inside the
RAMABLE_REGION.
Append h2ram_pool section at the end of used memory, so gap
due to alignment is still available for newly added variables.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Implement the hook for sys_poweroff based on the SOFT_OFF code. Note
that standby mode was a substate of SOFT_OFF, however, it was not
supported judging from defined DT states. It can be added later using
the STANDBY state.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Implement the sys_poweroff() hook. The hsem locking is not part of the
implementation, it doesn't seem necessary after
https://github.com/zephyrproject-rtos/zephyr/pull/42409 but I may be
wrong. Needs verification.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
SOFT_OFF state (which translates to standby) doesn't seem to be
supported according to the L0 DT files. Also, by definition soft off
implies context loss, ie boot from scratch, but the implementation
expected a call to the PM exit hook.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The second argument 'uint32_t *hpsram_pg_mask' must be a cached
pointer and this needs to be reflected in function prototype.
Fixes sparse warning:
/zep_workspace/zephyr/soc/xtensa/intel_adsp/cavs/power.c:106:63:
warning: incorrect type in argument 2 (different address spaces)
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Converting between cached and uncached aliases should have correct
sparse annotations. Fix following sparse warning:
/zep_workspace/zephyr/soc/xtensa/intel_adsp/cavs/power.c:97:53: warning:
incorrect type in argument 1 (different address spaces)
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
drivers: adc: adc_sam0: fix c20 and c21 reference not setting
On c20 and c21 variants, the adc_sam0 driver is failing to honor the
enable-protected status of the REFCTRL register when writing the channel
config's reference into it. This causes the reference to never be set
when adc_sam0_channel_setup is called since the ADC is not disabled
prior to the write. Fix it by adding the
ADC_SAM0_REFERENCE_ENABLE_PROTECTED definition to the c20 and c21 soc.h
files. This effectively disables the ADC during writes to the REFCTRL
register, thus honoring the enable-protected behavior of this register.
I'm assuming ADC_SAM0_REFERENCE_ENABLE_PROTECTED exists for this type
of situation and therefore this was the approach taken. After making
the change, I was able to verify proper ADC readings by measuring
voltage on an ADC pin and observing correct values. Reverting back prior
to this change, running the same test yields reading 0's.
Fixes: #61975
Signed-off-by: Tristen Pierson <tpierson@bitconcepts.tech>
System memory declared by the MPU as 'Strongly Ordered'
with region attributes which will inhibit the speculative fetch,
preventing the Flash RDSERR.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Use WAIT_FOR to wait for core power changes to be reflected
in status registers. If core power state does not complete in
10ms, k_panic() is raised.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Use WAIT_FOR to wait for clock source to be enabled. If clock does
not come up in 10ms, raise k_panic().
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Move workaround methods for npcx series to soc init functions. If
there's no workaround for this series, drop its soc.c file directly.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This adds SoC and board configs to support the dc233c core
that is available on QEMU. This core has more features than
sample_controller, such as MMU support.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This patch adds definitions for the nRF9131,
which is software-compatible with nRF9161.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
In case of stm32h5 both LL_DBGMCU_EnableTraceClock() and
LL_DBGMCU_SetTracePinAssignment() need to be called in order to properly
configure SWO output.
Select HAS_SWO, so that logging over SWO can be enabled.
Tested with ST's fork of openocd [1].
[1] https://github.com/STMicroelectronics/OpenOCD
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Update iMX RT boot header to support CONFIG_XIP=n, when the image is not
linked into the flash space. Also, update the boot header to correctly
calculate the flash used size within the boot data header. This field is
used by the iMX boot ROM to determine how much data to copy when running
from RAM, so using the correct size fixes an issue where the ROM would
copy more data than needed.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The CMSIS module glue code was part of arch/ directory. Move it to
modules/cmsis, and provide a single entry point for it: cmsis_core.h.
This entry header will include the right CMSIS header (M or A/R).
To make this change possible, CMSIS module Kconfig/CMake are declared as
external, allowing us to add a new Zephyr include directory.
All files including CMSIS have been updated.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This CL introduces new Flash Interface Unit (FIU) hardware in npcx4
series. The different operations of npcx9 and npcx4 FIU include:
1. 4-byte mode support for DRA mode move to SPI_DEV reg
2. To access the second flash in DRA mode, we need to configure
SPI_DEV_SEL field in BURST_CFG additionally.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This CL introduces new clock architectures in npcx4 series and wraps
clock configurations of different series by device tree files.
For example, the PWDWN_CTLx reg initialization relies on `pwdwn-ctl-val`
prop of pcc DT node now.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL adds the soc drivers for npcx4 series. Besides adding npcx4m3f
and npcx4m8f support, we also modified the register offset of
LV_GPIO_CTL and PUPD_EN for npcx4 series.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
With gcc from the zephyr sdk and -Wold-style-declaration is giving this
output:
zephyr/arch/arm/core/aarch32/cortex_a_r/fault.c:101:1: warning:
'inline' is not at beginning of declaration [-Wold-style-declaration]
101 | static void ALWAYS_INLINE
z_arm_fpu_caller_save(struct __fpu_sf *fpu)
| ^~~~~~
I searched to all of the source code to find these further occurances
where inline is not at the beginning of a function declaration.
Signed-off-by: Florian La Roche <Florian.LaRoche@gmail.com>
The XEC clock control driver sample code uses enum indexes to offset to
the desired GPIO CTRL register of the package. These enums are only
used in this example code and are being removed in favor of calculated
indexing into the specific GPIO register memory map.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
The existing heap starts at the beginning of SPIRAM which is also occupied
by the WiFi stack if CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM is enabled. This
results in memory corruption.
Update the linker description to add a _spiram_heap_start symbol and add a
KConfig size option to allow the SPIRAM stack to be correctly located and
sized. Requires matching commit in hal_espressif.
Fixes: 61359
Signed-off-by: Eric Holmberg <eric.holmberg@northriversystems.co.nz>
This enables -Wshadow to warn about shadow variables on
in tree code under arch/, boards/, drivers/, kernel/,
lib/, soc/, and subsys/.
Note that this does not enable it globally because
out-of-tree modules will probably take some time to fix
(or not at all depending on the project), and it would be
great to avoid introduction of any new shadow variables
in the meantime.
Also note that this tries to be done in a minimally
invasive way so it is easy to revert when we enable
-Wshadow globally. Source files under modules/, samples/
and tests/ are currently excluded because there does not
seem to be a trivial way to add -Wshadow there without
going through all CMakeLists.txt to add the option
(as there are 1000+ files to change).
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
For some weird reasons, if the sections in linker script are not
in memory address order, there are lots of padding involved in
zephyr_pre0.elf. This moves the .intList section to its memory
ordered location. When building hello_world, this shrinks
zephyr_pre0.elf from 512MB to 339KB.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The current mechanism of the MPU region switching configures and
reprograms the regions (including inserting, splitting the dynamic
region, and flushing the regions to the registers) every time during the
context switch. This, not only causes a large usage of the kernel stack
but also a lower performance.
To improve it, move the configuration operations ahead to make sure the
context swtich only flushes the current thread regions to the registers
and does not configure the regions anymore. To achieve this, configure
the regions during any operations related to partitions (partition
add/remove, and domain add/remove thread), flush the sys_dyn_regions if
the current thread is the privileged thread, and flush the thread's own
regions if it's a user thread.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
This enables the power management for Intel ISH. It supports D0i1,
D0i2, D0i3 power saving modes for ISH.
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
Move arm_mpu_mem_cfg header to common include directory.
The benefits are two-fold:
- Allow for out of tree SoC definitions to use them to
define mpu_regions.
- Remove odd relative include path
Signed-off-by: Moritz Fischer <moritzf@google.com>
Reduce the main clock frequency from 150MHz to 144MHz which allows meeting
the full range of CAN bitrates.
Fixes: #60811
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Implement the sys_poweroff hook for all ESP32 SoCs based on the previous
SOFT_OFF implementation.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Since bb590b5b6e, which enforces a more consistent ordering of
initialisation for devices, the ECIA initialisation was happening after
GPIO initialisation. This caused interrupts to stop working on GPIO
input.
This patch fixes that by increasing the default GPIO initialisation
priority, so that it happens after ECIA.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Since bb590b5b6e, which enforces a more consistent ordering of
initialisation for devices, the SOC initialisation was happening after
GPIO initialisation. This caused interrupts to stop working on GPIO
input.
This patch fixes that by increasing the default GPIO initialisation
priority, so that it happens after SOC.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
openamp shared memory regions can be anywhere in DDR memory
withing 2G range. Current SRAM_PRIV region is 64M which
prevents access of shared memory (vrings) by RPU (cortex-r5)
if it is out of 64M range. This patch allows vrings to be in DDR within
2G address space.
Developed-by: Dan Millea
Commited by: Tanmay Shah
Signed-off-by: Dan Milea <dan.milea@windriver.com>
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Configure ENET_REF_CLK direction as input when
CONFIG_ETH_MCUX_RMII_EXT_CLK is set to allow Ethernet external clock
usage.
Signed-off-by: Benjamin Lemouzy <blemouzy@centralp.fr>
In case of HDA Link DMA FIFORDY bit is RO according
to HW specification thus should be managed by HDA controller.
Add a logic to set FIFORDY for HDA Host DMA only
Signed-off-by: Ievgen Ganakov <ievgen.ganakov@intel.com>
SiLabs' sleeptimer driver supports several hardware peripherals, of
which the counter driver so far only supports the RTCC-based variant.
This patch adds support for the SYSRTC-based sleeptimer implementation,
which is required for Gecko SoCs that do not have an RTCC module.
Signed-off-by: Markus Fuchs <markus.fuchs@ch.sauter-bc.com>
nRF53/91 require usage of nrf_regulators_system_off, so the API is not
common with nRF51/52. This was an oversight during the conversion.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Adds support for the NXP VMU RT1170 board. This Vehicle
Management Unit based on the i.MX RT1176 brings a fantastic
combination of sensors and IO all on one board for development
of various systems. It is also the featured board for
CogniPilot's Cerebri - VMU autopilot software based on Zephyr.
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Remove CONFIG_OCRAM_NOCACHE setting, as this is now possible to achieve
using devicetree linker regions, and there is no point in having a
specific Kconfig for one memory region on the RT series like this.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable SOC fixed MPU regions by default for the RT10xx/RT11xx SOC lines.
Additionally, add code to handle defining the SDRAM0 region as
device type (non cacheable, non shareable). This behavior can
be disabled with CONFIG_NXP_IMX_EXTERNAL_SDRAM=y. Set this Kconfig
for all boards in tree using SDRAM.
This will resolve an issue present on the RT11xx series where
the core may execute speculative prefetches to the SDRAM region when
no SDRAM is present on the board, resulting in the system faulting.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Don't default CONFIG_DEVICE_CONFIGURATION_DATA to enabled for iMX RT
SOCs, as this configuration block is only used when the board needs
peripherals like the external memory controller setup from reset by the
bootrom.
Enable this feature on all in tree boards that will require it,
and document the change to the default value in release notes.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Nordic SoCs do all power management automagically when going to idle (ie
k_cpu_idle()). The only extra state, system off, is now handled via
sys_shutdown(), so there's no need to support the PM subsystem.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
So far the init priories were:
enetc_psi0=60 < enetc_vsin=61 < emdio=70 < ethernet-phy=80
because the Ethernet PSI driver was doing global initialization for the
whole NETC complex, including enabling MDIO function (due to the way
the HAL works).
Change to use the default init priorities:
mdio=60 < phy=70 < eth=enetc_psi0=80 < enetc_vsin=81
by executing at an early stage the NETC global initialization. This also
allows to match the DT hierarchy representation of NETC with the
effective priorities assigned.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Disable SysTick when STIMER is in use and configure
SYS_CLOCK_HW_CYCLES_PER_SEC setting for it.
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
This commit addst pinctrl support for Apollo4 SoCs.
Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
The sam0 CMCC configure Cortex-M cache controller. However, it is not
clear how the cache management should be performed. It is nor clear if
instructions like SCB_EnableICache can be used. In this case, if cache
management should be made only by CMCC it may require a dedicated
implementation.
Besides above, the CPU_CORTEX_M4 do not define cache by default which
can signal a bad configuration in tree since the SOC_SERIES_SAME54 do
not define which caches should be available.
This force cache controller disable to avoid issues.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The current platform initialization do not take in consideration cache
management for historic reasons. This fixes any miss configuration and
allow users to enable/disable caches at board definition. The default
value is cache disabled and the below examples are for SAMV71 which
have both I/D Cache available:
I Cache only:
CONFIG_CACHE_MANAGEMENT=y
CONFIG_DCACHE=n
D Cache only:
CONFIG_CACHE_MANAGEMENT=y
CONFIG_ICACHE=n
I/D Cache disabled:
CONFIG_ICACHE=n
CONFIG_DCACHE=n
I/D Cache Enabled:
CONFIG_CACHE_MANAGEMENT=y
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This replace pre kernel initialization by the platform specific
initialization call. The platform specific init will configure
at very beginning the clocks, flash wait states and cache.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update Kconfig.series files to normalize copyright date order from
lower to higher and reorder select entries.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
File was using stdint.h defined types without including and caused a
build error depending on include ordering.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Some configurations have the system timer driver hardwired in.
Let's make them compatible with CONFIG_SYS_CLOCK_EXISTS=n.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This device has a single instance of EMAC (a 100Mbps version of GMAC).
TCP/UDP checksum calculation is offloaded.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Reuse existing NXP LPSPI binding for this SoC since the hardware block
for this device is the same as the one supported for other NXP devices.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Do not select CONFIG_CACHE_MANAGEMENT in the Microchip SAM CAN driver
Kconfig but rather leave it up to the SoC/platform Kconfig to enable it as
needed and enable CACHE_MANAGEMENT by default for the Atmel SAM E70/V71 SoC
series.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Currently on zephyr, RAIL is used only for bluetooth. RAIL library is
needed to use efr32 radio regardless of the protocol used. We add
SOC_GECKO_USE_RAIL kconfig option to indicate if we use radio.
FPU is needed when using RAIL, we configure it if SOC_GECKO_USE_RAIL
is set.
Signed-off-by: Antoine Bout <antoine.bout@silabs.com>
Add an option to control whether or not hpsram banks should
be switched off during the power down. This is particular useful
when running tests because we don't want to lose the contents
of the memory window before we capture it.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Update to shim driver compatible with the hardware block
in S32K344. Configure the pins before initializing I2C
to avoid happening bus busy.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Reuse existing MCUX-based shim driver for FlexCAN.
Enable flexcan0 for Zephyr canbus to run tests.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Adds driver for pwm on xmc4xxx using Capture Compare Unit 8 (CCU8)
module. There are two CCU8 nodes with each one having four slices.
Each slice has two output channels.
Unlike CCU4, this module can generate complementary high-side/low-side
signals for each output channel. A variable dead time can be added
during the off to on transitions to make sure that the
high-side/low-side signals are not on at the same time.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Adds driver for pwm on xmc4xxx using Capture Compare Unit 4 (CCU4)
module. There are four CCU4 with each one having four channels
Thus it's possible to have up to 16 pwm output signals. The output of
each channel can only be connected to a specific port/pin. The possible
connection and gpio configurations are defined using pinctrl.
The CCU4 module also has a capture mode. Capture support will be added
in the future.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Pinmuxing is now done by a pinctrl driver, not by board.c,
so the code used previously for pinmuxing can be removed.
Fixes#59186.
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
Introduces support for SoC-specific input-edge-detect configuration to
the CC13/26xx pinctrl driver.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
CC13/26xx's pinctrl_cc13xx_cc26xx.c driver included ioc.h and
(indirectly) pinctrl_soc.h which contained duplicate defines.
This change removes the header conflict and redundant definitions.
This prepares for subsequent changes in this change set that add
additional flags to the pinctrl driver which would otherwise trigger the
header conflict.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
Add Kconfig RISCV_SOC_HAS_CUSTOM_SYS_IO symbol so that a riscv
SoC can set to specify that it has a custom implementation for
sys_io functions.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:
- changing the CONFIG_SOC_ESP32* to refer to
the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
provide a SOC model config
- introducing the 'common' folder to hide all
commonly used configs and files.
- updating west.yml to reflect previous changes in hal
Signed-off-by: Marek Matej <marek.matej@espressif.com>
- use CONFIG_HAS_HW_NRF_* symbols consistently in nRF multi-instance
drivers when creating particular driver instances
- remove unnecessary hidden Kconfig options that indicated the type of
peripheral to be used by a given instance (e.g. SPI, SPIM, or SPIS)
and enabled proper nrfx driver instance; instead, use one option per
peripheral type and include the corresponding shim driver flavor into
compilation basing on that option (not the one that enables the nrfx
driver as it was incorrectly done so far in some cases)
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Some EFR32 build broke after 3d2194f11e with:
pm.c:152: undefined reference to `pm_state_exit_post_ops'
Add an extra empty function to make this one build again.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Added dts additions for stm32f105xb cpu which is the same as existing
stm32f105xc with less flash.
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
The Keystone 3 (K3) family encompasses a wider variety of SoC's.
This aligns the soc/arm64 naming with the soc/arm directory.
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
This CL attempts to implement npcx's flash driver instead of the
original one (npcx spi driver plus spi_nor flash driver).
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add a new pinctrl type to control peripheral modules' specific IO
characteristics such as tri-state, the power supply type selection (3.3V
or 1.8V), and so on. In NPCX series, the corresponding registers/fields
are irregular. This CL wraps these definitions to dt nodes and put them
in pinctrl property if needed.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The PM hooks were guarded with CONFIG_PM_POLICY_CUSTOM, however, they
need to be guarded (if file is always compiled) with CONFIG_PM. In fact,
CONFIG_PM_POLICY_CUSTOM requires to implement a custom policy hook,
something this module did not provide.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Remove unnecessary __weak attribute from power management functions.
These functions are now defined once, globally, and mandatory for
systems that support CONFIG_PM.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add a new Kconfig option that has to be selected by SoCs providing PM
hooks. This option will be now required to enable CONFIG_PM. Before this
change, CONFIG_PM could always be enabled, regardless of SoC providing
any kind of low-power support.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The clock rates for ACE series of Intel Audio DSP have changed.
The values come from the SOF project in their board configs.
CONFIG_XTENSA_CCOUNT_HZ is also set so the arch timing test
can pass.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Updated the clock init to reflect the sdk also
updated the clock frequencies to reflect the
respective soc clock values, this file originally
contained unexpected clock values, updated comments
to reflect changes and got rid of doxygen style
comments
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Add CONFIG_SOC_ANDES_V5_IOCP to indicate Andes I/O Coherence Port handle
cache coherency between cache and external non-caching master, such as DMA
controller.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Andes EXEC.IT (Execution on Instruction Table) is supported by Andes
toolchain only. Andes toolchain will replaces suitable 32-bit instructions
with the 16-bit "exec.it <INDEX>" in which <INDEX> points to a
corresponding 32-bit instruction in look up table.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Enable PMP and set PMP granularity to 8 for most of ae350 bitstream.
This commit also make MPU_ALIGN() apply to __rom_region_end in XIP system.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Refine PMA driver and define MPU_ALIGN() to PMA granularity in
RAM_SECTIONS, otherwise MPU_ALIGN() is defined to PMP granularity.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Synchronize ae350 linker.ld with riscv generic linker.ld and workaround
kernel object address may be 0x0 in XIP system.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Align `soc/nxp_adsp` with new `WEST_SIGN_OPTS` option added to
`soc/intel_adsp` by recent commit d98a7c2f8d ("soc: xtensa: cmake: add
new WEST_SIGN_OPTS variable").
This allows per-board rimage customization at the CMake level. Example
in `zephyr/boards/xtensa/nxp_adsp_NEWBOARD/board.cmake`:
set(WEST_SIGN_OPTS -- -c rimage/config/special.toml)
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
With NEORV32 v1.8.2 the UART module was changed to a simpler
implementation. This updates the UART driver for the open-source NEORV32
RISC-V compatible processor system (SOC).
Signed-off-by: Tim-Marek Thomas <thomas@sra.uni-hannover.de>
Add I2C target driver used buffer mode. The maximum accessible buffer
is 2044 bytes, the default is 256 bytes.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add Pin Function Controller tables of registers and their bits
for ARM64 Renesas R-Car family. With this changes we can use
Renesas PFC driver for configuring bias and driving capabilities.
Add only needed driver strength and bias pins to PFC,
e.g. SDx and UART TX/RX pins.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Add support of r8a77961 SoC to gen3 series.
Create a dtsi file with a common part for both r8a77951 and r8a77961.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Add Pin Function Controller tables of registers and their bits
for ARM64 Renesas R-Car family. With this changes we can use
Renesas PFC driver for configuring bias and driving capabilities.
Note: some of files copy-pasted from Renesas Arm 32
SoC directory and this commit is a temporary
solution, we need to rework it in order to use
the same source files for both architectures.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
- This includes the driver, test app, and sample app
- Only the boards\arm\xmc47_relax_kit board is supported for now
Signed-off-by: Bill Waters <bill.waters@infineon.com>
Instead of relying on direct memory access via structs to
control CPU power and status, using inline functions instead
to hide the details. This makes reading the common code a bit
cleaner.
The function names are generic and not architecture or
platform specific, in an attempt to ease future arch or
platform additions with code reuse. Or else we would need to
rename these.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Some boards has ESP_SPIRAM enabled by default, which is
causing issues when MCUboot is used as 2nd bootloader.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
This fixes the following build error:
```
zephyr/zephyr.elf', needed by 'zephyr/zephyr.ri', missing and no known
rule to make it
```
This appears when CONFIG_KERNEL_BIN_NAME is used.
Therefore, do not use zephyr.elf since some samples might be called
based on CONFIG_KERNEL_BIN_NAME.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Removes duplicate code and inconsistencies in the naming of the
cc13xx_cc26xx devicetree and RTC driver hierarchy and alignes it with
the actual TI product series naming hierarchy.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
On nRF5340 net core it was observed that when `wfi` instruction was
followed by `pop {r0, lr}` in the `arch_cpu_idle` function,
the value of `lr` sometimes got read as 0 from memory despite
having correct value stored in the memory.
This commit inserts additional `nop` instruction after waking up
to delay access to the memory.
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
Reuse existing MCUX-based shim driver for LPUART that is compatible with
the hardware block in S32K344. DMA is not yet supported.
Use the board's debug connector (P6 / LPUART2) as default console.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Unify the pinctrl_soc.h header for all the NXP S32 family by using
the HAL macros that expose the features supported on specific
devices. This approach still need a different binding for each device to
expose in DT different properties and allowed values.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Introduce minimal power initialization for NXP S32 SoCs and allow to
reset the SoC through the sys_reboot() API.
Presently only S32K3 SoCs is supported but it can be extended later to
other NXP S32 SoCs, hence it's placed in a common directory.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The S32K3 MCUs are 32-bit Arm Cortex-M7-based microcontrollers with a
focus on automotive and industrial applications. The S32K344 features
a lock-step core, internal flash, RAM and TCM with ECC.
Co-authored-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Co-authored-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
NMI_INIT() is now a no-op, so remove it from all SoC code. Also remove
the irq lock/unlock pattern as it was likely a cause of copy&paste when
NMI_INIT() was called.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This patch sets ENET2 ref clock to be generated by External OSC
ENET2 ref clock direction as output
ENET2 ref clk frequency to 50MHz
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
The Zephyr linker scripts have inconsistent ordering of various chunks of
data which lands in RAM at runtime. This leads to the value of _end not
being consistently defined as the maximum address of static variables used
in the application.
Create a helper linker fragment, zephyr/linker/ram-end.ld, which can be
included after the last possible definition of RAM data, that consistently
sets _image_ram_end, _end and z_mapped_end.
Signed-off-by: Keith Packard <keithp@keithp.com>
After exiting D3 state if IMR context save is enabled, IDC interrupt
must be re-enabled again for all cores.
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
The ifdefs in in dmic headers is getting out of control and makes
maintainence very ddifficult, especially when having to maintain out of
tree SoCs sharing the same data and information.
Keep header clean and per SoC and share some common registers in one
place instead avoiding confusion and making it easier to read and
maintain.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Where the bottom is the only one which interacts with
the host operating system.
And the top the only one that interacts or is aware
of the hosted operating system (Zephyr).
The bottom uses the native simulator CPU
start/stop emulation.
By now we replicate its code as a provisional measure,
until the native simulator becomes standard.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Where the bottom is the only one which interacts with
the host operating system, and does not necessarily
need to know about the Zephyr OS.
This is in preparation for the native simulator,
which which the bottom is also fully Zephy agnostic.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
A known issue exists that does not allow a CC13/26x2R device to
establish a link to a CC13/26x2P device unless the capacitor array is
tuned to a non-default value in the P device.
See SimpleLink(TM) cc13xx_cc26xx SDK 6.20+ Release Notes, Known Issues.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
The native_tasks logic is unrelated to the remaining
of the soc logic (which handles CPU start/stopping)
refactor it out into its own file.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Let's remove the native_posix part from the SOC description
and just refer to "native".
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The native_tasks header requires the toolchain header.
Let's include it directly instead of requiring users
of this header to include it before.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
When CONFIG_PM_DEVICE is enabled IPC Device may be during power transition
during a call to intel_adsp_ipc_send_message function.
Changed signatures of intel_adsp_ipc_send_message and its sync version
to return int and negative error codes on error.
On attempt to send IPC message during Device power transition
-ESHUTDOWN error code is returned, on busy state -EBUSY.
Updated all function references.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
When option CONFIG_PM_DEVICE is enabled, IPC driver is capable
of entering D3 power state described as PM_DEVICE_ACTION_SUSPEND
(and leaving that state - powering back to PM_DEVICE_ACTION_ACTIVE).
New power control callbacks 'ipc_power_control_api' are introduced for
use during power state transisions. They allow Zephyr application
specific code to be executed.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
Exiting idle state requires to reinitialize all memory window
instances to flush the cached memory.
Added function that calls initialization of devices during runtime.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
Generic header for system clock allows to define a sys_clock_idle_exit
function for the clock implementation.
Implemented the function in the intel_adsp_timer to reinitialize
device driver after the idle exit state.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
Provides a way to use pinctrl to allow internal loopback
on a peripheral pin for testing purposes.
This is done by using output-enable on a input pin and
input-enable on a output pin.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
All Cortex-M processors can support RTT by default. This change enables
RTT support for the cc13xx/cc26xx SoC series (tested in hardware on
CC1352R).
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
Add Nuvoton numaker series clock controller support, including:
1. Do system clock initialization in z_arm_platform_init().
2. Support peripheral clock control API equivalent to BSP
CLK_EnableModuleClock()/CLK_SetModuleClock().
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Added a new function to check whether a clock source is supported by a
platform and to retrieve its frequency.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
The word cpu was added to the names of functions, structs, types
and definitions to disambiguate the names and make room in the namespace
for soc clock control functions.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Add simple mechanism to load the image from IMR memory. Basically we are
only setting a flag in power off for the next boot to jump to existing
image in IMR.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>