soc: quicklogic_eos_s3: remove unneeded code
Pinmuxing is now done by a pinctrl driver, not by board.c, so the code used previously for pinmuxing can be removed. Fixes #59186. Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
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3 changed files with 0 additions and 28 deletions
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@ -20,20 +20,6 @@ void eos_s3_lock_disable(void)
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MISC_CTRL->LOCK_KEY_CTRL = 1;
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}
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int eos_s3_io_mux(uint32_t pad_nr, uint32_t pad_cfg)
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{
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volatile uint32_t *p = (uint32_t *)IO_MUX_BASE;
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if (pad_nr > EOS_S3_MAX_PAD_NR) {
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return -EINVAL;
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}
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p += pad_nr;
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*p = pad_cfg;
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return 0;
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}
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static void eos_s3_cru_init(void)
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{
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/* Set desired frequency */
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@ -46,11 +46,7 @@
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#define OSC_SET_FREQ_INC(FREQ) (AIP->OSC_CTRL_1 = ((FREQ / 32768) - 3) & 0xFFF)
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#define OSC_GET_FREQ_INC() (((AIP->OSC_CTRL_1 & 0xFFF) + 3) * 32768)
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#define EOS_S3_MAX_PAD_NR 45
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void eos_s3_lock_enable(void);
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void eos_s3_lock_disable(void);
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int eos_s3_io_mux(uint32_t pad_nr, uint32_t pad_cfg);
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#endif /* _SOC__H_ */
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@ -9,14 +9,4 @@
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#include <soc.h>
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/* Set UART TX to PAD44 */
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#define UART_TXD_PAD44 (UART_TXD_SEL_PAD44 | PAD_CTRL_SEL_AO_REG \
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| PAD_OEN_NORMAL | PAD_P_Z | PAD_SR_SLOW \
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| PAD_E_4MA | PAD_REN_DISABLE | PAD_SMT_DISABLE)
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/* Set UART RX to PAD45 */
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#define UART_RXD_PAD45 (UART_RXD_SEL_PAD45 | PAD_CTRL_SEL_AO_REG \
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| PAD_OEN_DISABLE | PAD_P_Z | PAD_SR_SLOW \
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| PAD_E_4MA | PAD_REN_ENABLE | PAD_SMT_DISABLE)
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#endif /* _QUICKLOGIC_EOS_S3_SOC_PINMAP_H_ */
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