soc: npcx: add soc drivers for npcx4 series

This CL adds the soc drivers for npcx4 series. Besides adding npcx4m3f
and npcx4m8f support, we also modified the register offset of
LV_GPIO_CTL and PUPD_EN for npcx4 series.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This commit is contained in:
Mulin Chao 2023-05-02 02:28:18 -07:00 committed by Fabio Baltieri
commit 8ae0bb8b70
14 changed files with 161 additions and 11 deletions

View file

@ -42,6 +42,8 @@ config NPCX_HEADER_CHIP
default "npcx9m3" if SOC_NPCX9M3F
default "npcx9m6" if SOC_NPCX9M6F
default "npcx9m7" if SOC_NPCX9M7F
default "npcx4m3" if SOC_NPCX4M3F
default "npcx4m8" if SOC_NPCX4M8F
choice NPCX_HEADER_SPI_MAX_CLOCK_CHOICE
prompt "Clock rate to use for SPI flash"

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@ -213,8 +213,8 @@ def _check_chip(output, ecst_args):
if ecst_args.chip_name == INVALID_INPUT:
message = f'Invalid chip name, '
message += "should be npcx9m8, npcx9m7, npcx9m6, npcx7m7," \
" npcx7m6, npcx7m5, npcx5m5 or npcx5m6."
message += "should be npcx4m3, npcx4m8, npcx9m8, npcx9m7, npcx9m6, " \
"npcx7m7, npcx7m6, npcx7m5."
_exit_with_failure_delete_file(output, message)
def _set_anchor(output, ecst_args):
@ -924,7 +924,7 @@ def _crc_update(cur, crc, table):
:param crc
:param table
"""
l_crc = (0x000000ff & cur)
l_crc = 0x000000ff & cur
tmp = crc ^ l_crc
crc = (crc >> 8) ^ table[(tmp & 0xff)]

View file

@ -53,6 +53,8 @@ CHIPS_INFO = {
'npcx9m3': {'ram_address': 0x10080000, 'ram_size': 0x50000},
'npcx9m6': {'ram_address': 0x10090000, 'ram_size': 0x40000},
'npcx9m7': {'ram_address': 0x10070000, 'ram_size': 0x60000},
'npcx4m3': {'ram_address': 0x10088000, 'ram_size': 0x50000},
'npcx4m8': {'ram_address': 0x10060000, 'ram_size': 0x7c800},
}
DEFAULT_CHIP = 'npcx7m6'

View file

@ -241,15 +241,23 @@ static inline uint32_t npcx_devalt_lk_offset(uint32_t alt_lk_no)
static inline uint32_t npcx_pupd_en_offset(uint32_t pupd_en_no)
{
return 0x28 + pupd_en_no;
if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7) || IS_ENABLED(CONFIG_SOC_SERIES_NPCX9)) {
return 0x28 + pupd_en_no;
} else { /* NPCX4 and later series */
return 0x2b + pupd_en_no;
}
}
static inline uint32_t npcx_lv_gpio_ctl_offset(uint32_t ctl_no)
{
if (ctl_no < 5) {
return 0x02a + ctl_no;
} else {
return 0x026 + ctl_no - 5;
if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7) || IS_ENABLED(CONFIG_SOC_SERIES_NPCX9)) {
if (ctl_no < 5) {
return 0x02a + ctl_no;
} else {
return 0x026 + ctl_no - 5;
}
} else { /* NPCX4 and later series */
return 0x150 + ctl_no;
}
}

View file

@ -44,11 +44,11 @@ struct npcx_clk_cfg {
#define APB3DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb3_prescaler) - 1)
/* APB4 clock divider if supported */
#if DT_NODE_HAS_PROP(DT_NODELABEL(pcc), apb4_prescaler)
#if defined(CONFIG_SOC_SERIES_NPCX9)
#if !defined(CONFIG_SOC_SERIES_NPCX7) /* Supported in NPCX9 and later series */
#define APB4DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb4_prescaler) - 1)
#else
#error "APB4 clock divider is not supported but defined in pcc node!"
#endif
#endif /* !CONFIG_SOC_SERIES_NPCX7 */
#endif
/*
@ -101,7 +101,10 @@ struct npcx_clk_cfg {
#else
#define HFCGN_VAL 0x02
#endif
#if (OFMCLK == 100000000)
#if (OFMCLK == 120000000)
#define HFCGMH_VAL 0x0E
#define HFCGML_VAL 0x4E
#elif (OFMCLK == 100000000)
#define HFCGMH_VAL 0x0B
#define HFCGML_VAL 0xEC
#elif (OFMCLK == 96000000)

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@ -0,0 +1,7 @@
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(${ZEPHYR_BASE}/drivers)
zephyr_sources(
soc.c
)

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@ -0,0 +1,11 @@
# Nuvoton Cortex-M4 Embedded Controller
# Copyright (c) 2023 Nuvoton Technology Corporation.
# SPDX-License-Identifier: Apache-2.0
if SOC_NPCX4M3F
config SOC
default "npcx4m3f"
endif # SOC_NPCX4M3F

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@ -0,0 +1,11 @@
# Nuvoton Cortex-M4 Embedded Controller
# Copyright (c) 2023 Nuvoton Technology Corporation.
# SPDX-License-Identifier: Apache-2.0
if SOC_NPCX4M8F
config SOC
default "npcx4m8f"
endif # SOC_NPCX4M8F

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@ -0,0 +1,23 @@
# Nuvoton Cortex-M4 Embedded Controller
# Copyright (c) 2023 Nuvoton Technology Corporation.
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_NPCX4
config SOC_SERIES
default "npcx4"
config NUM_IRQS
default 128
config CORTEX_M_SYSTICK
default !NPCX_ITIM_TIMER
config ESPI_NPCX
default y
depends on ESPI
source "soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4*"
endif # SOC_SERIES_NPCX4

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@ -0,0 +1,15 @@
# Nuvoton Cortex-M4 Embedded Controller NPCX4 series
# Copyright (c) 2023 Nuvoton Technology Corporation.
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_NPCX4
bool "Nuvoton NPCX4 Series"
select ARM
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select CPU_HAS_ARM_MPU
select SOC_FAMILY_NPCX
help
Enable support for Nuvoton NPCX4 series

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@ -0,0 +1,16 @@
# Nuvoton NPCX4 EC series
# Copyright (c) 2023 Nuvoton Technology Corporation.
# SPDX-License-Identifier: Apache-2.0
choice
prompt "NPCX4 Selection"
depends on SOC_SERIES_NPCX4
config SOC_NPCX4M3F
bool "NPCX4M3F"
config SOC_NPCX4M8F
bool "NPCX4M8F"
endchoice

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@ -0,0 +1,9 @@
/* linker.ld - Linker command/script file */
/*
* Copyright (c) 2023 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/arch/arm/aarch32/cortex_m/scripts/linker.ld>

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@ -0,0 +1,21 @@
/*
* Copyright (c) 2023 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
static int soc_init(void)
{
return 0;
}
SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

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@ -0,0 +1,22 @@
/*
* Copyright (c) 2023 Nuvoton Technology Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _NUVOTON_NPCX_SOC_H_
#define _NUVOTON_NPCX_SOC_H_
/* CMSIS required definitions */
#define __FPU_PRESENT CONFIG_CPU_HAS_FPU
#define __MPU_PRESENT CONFIG_CPU_HAS_ARM_MPU
#include <reg/reg_access.h>
#include <reg/reg_def.h>
#include <soc_dt.h>
#include <soc_clock.h>
#include <soc_pins.h>
#include <soc_power.h>
#endif /* _NUVOTON_NPCX_SOC_H_ */