soc: npcx: add soc drivers for npcx4 series
This CL adds the soc drivers for npcx4 series. Besides adding npcx4m3f and npcx4m8f support, we also modified the register offset of LV_GPIO_CTL and PUPD_EN for npcx4 series. Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
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f380f8200c
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14 changed files with 161 additions and 11 deletions
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@ -42,6 +42,8 @@ config NPCX_HEADER_CHIP
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default "npcx9m3" if SOC_NPCX9M3F
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default "npcx9m6" if SOC_NPCX9M6F
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default "npcx9m7" if SOC_NPCX9M7F
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default "npcx4m3" if SOC_NPCX4M3F
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default "npcx4m8" if SOC_NPCX4M8F
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choice NPCX_HEADER_SPI_MAX_CLOCK_CHOICE
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prompt "Clock rate to use for SPI flash"
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@ -213,8 +213,8 @@ def _check_chip(output, ecst_args):
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if ecst_args.chip_name == INVALID_INPUT:
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message = f'Invalid chip name, '
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message += "should be npcx9m8, npcx9m7, npcx9m6, npcx7m7," \
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" npcx7m6, npcx7m5, npcx5m5 or npcx5m6."
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message += "should be npcx4m3, npcx4m8, npcx9m8, npcx9m7, npcx9m6, " \
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"npcx7m7, npcx7m6, npcx7m5."
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_exit_with_failure_delete_file(output, message)
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def _set_anchor(output, ecst_args):
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@ -924,7 +924,7 @@ def _crc_update(cur, crc, table):
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:param crc
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:param table
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"""
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l_crc = (0x000000ff & cur)
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l_crc = 0x000000ff & cur
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tmp = crc ^ l_crc
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crc = (crc >> 8) ^ table[(tmp & 0xff)]
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@ -53,6 +53,8 @@ CHIPS_INFO = {
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'npcx9m3': {'ram_address': 0x10080000, 'ram_size': 0x50000},
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'npcx9m6': {'ram_address': 0x10090000, 'ram_size': 0x40000},
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'npcx9m7': {'ram_address': 0x10070000, 'ram_size': 0x60000},
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'npcx4m3': {'ram_address': 0x10088000, 'ram_size': 0x50000},
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'npcx4m8': {'ram_address': 0x10060000, 'ram_size': 0x7c800},
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}
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DEFAULT_CHIP = 'npcx7m6'
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@ -241,15 +241,23 @@ static inline uint32_t npcx_devalt_lk_offset(uint32_t alt_lk_no)
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static inline uint32_t npcx_pupd_en_offset(uint32_t pupd_en_no)
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{
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return 0x28 + pupd_en_no;
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if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7) || IS_ENABLED(CONFIG_SOC_SERIES_NPCX9)) {
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return 0x28 + pupd_en_no;
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} else { /* NPCX4 and later series */
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return 0x2b + pupd_en_no;
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}
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}
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static inline uint32_t npcx_lv_gpio_ctl_offset(uint32_t ctl_no)
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{
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if (ctl_no < 5) {
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return 0x02a + ctl_no;
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} else {
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return 0x026 + ctl_no - 5;
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if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7) || IS_ENABLED(CONFIG_SOC_SERIES_NPCX9)) {
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if (ctl_no < 5) {
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return 0x02a + ctl_no;
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} else {
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return 0x026 + ctl_no - 5;
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}
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} else { /* NPCX4 and later series */
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return 0x150 + ctl_no;
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}
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}
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@ -44,11 +44,11 @@ struct npcx_clk_cfg {
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#define APB3DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb3_prescaler) - 1)
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/* APB4 clock divider if supported */
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#if DT_NODE_HAS_PROP(DT_NODELABEL(pcc), apb4_prescaler)
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#if defined(CONFIG_SOC_SERIES_NPCX9)
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#if !defined(CONFIG_SOC_SERIES_NPCX7) /* Supported in NPCX9 and later series */
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#define APB4DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb4_prescaler) - 1)
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#else
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#error "APB4 clock divider is not supported but defined in pcc node!"
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#endif
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#endif /* !CONFIG_SOC_SERIES_NPCX7 */
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#endif
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/*
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@ -101,7 +101,10 @@ struct npcx_clk_cfg {
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#else
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#define HFCGN_VAL 0x02
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#endif
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#if (OFMCLK == 100000000)
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#if (OFMCLK == 120000000)
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#define HFCGMH_VAL 0x0E
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#define HFCGML_VAL 0x4E
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#elif (OFMCLK == 100000000)
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#define HFCGMH_VAL 0x0B
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#define HFCGML_VAL 0xEC
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#elif (OFMCLK == 96000000)
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7
soc/arm/nuvoton_npcx/npcx4/CMakeLists.txt
Normal file
7
soc/arm/nuvoton_npcx/npcx4/CMakeLists.txt
Normal file
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@ -0,0 +1,7 @@
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# SPDX-License-Identifier: Apache-2.0
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zephyr_include_directories(${ZEPHYR_BASE}/drivers)
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zephyr_sources(
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soc.c
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)
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11
soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4m3f
Normal file
11
soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4m3f
Normal file
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@ -0,0 +1,11 @@
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# Nuvoton Cortex-M4 Embedded Controller
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# Copyright (c) 2023 Nuvoton Technology Corporation.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_NPCX4M3F
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config SOC
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default "npcx4m3f"
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endif # SOC_NPCX4M3F
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11
soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4m8f
Normal file
11
soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4m8f
Normal file
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@ -0,0 +1,11 @@
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# Nuvoton Cortex-M4 Embedded Controller
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# Copyright (c) 2023 Nuvoton Technology Corporation.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_NPCX4M8F
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config SOC
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default "npcx4m8f"
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endif # SOC_NPCX4M8F
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23
soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.series
Normal file
23
soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.series
Normal file
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@ -0,0 +1,23 @@
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# Nuvoton Cortex-M4 Embedded Controller
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# Copyright (c) 2023 Nuvoton Technology Corporation.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_NPCX4
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config SOC_SERIES
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default "npcx4"
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config NUM_IRQS
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default 128
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config CORTEX_M_SYSTICK
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default !NPCX_ITIM_TIMER
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config ESPI_NPCX
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default y
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depends on ESPI
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source "soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4*"
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endif # SOC_SERIES_NPCX4
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15
soc/arm/nuvoton_npcx/npcx4/Kconfig.series
Normal file
15
soc/arm/nuvoton_npcx/npcx4/Kconfig.series
Normal file
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@ -0,0 +1,15 @@
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# Nuvoton Cortex-M4 Embedded Controller NPCX4 series
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# Copyright (c) 2023 Nuvoton Technology Corporation.
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_NPCX4
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bool "Nuvoton NPCX4 Series"
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select ARM
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select CPU_CORTEX_M4
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_FPU
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select CPU_HAS_ARM_MPU
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select SOC_FAMILY_NPCX
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help
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Enable support for Nuvoton NPCX4 series
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soc/arm/nuvoton_npcx/npcx4/Kconfig.soc
Normal file
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soc/arm/nuvoton_npcx/npcx4/Kconfig.soc
Normal file
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@ -0,0 +1,16 @@
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# Nuvoton NPCX4 EC series
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# Copyright (c) 2023 Nuvoton Technology Corporation.
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# SPDX-License-Identifier: Apache-2.0
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choice
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prompt "NPCX4 Selection"
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depends on SOC_SERIES_NPCX4
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config SOC_NPCX4M3F
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bool "NPCX4M3F"
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config SOC_NPCX4M8F
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bool "NPCX4M8F"
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endchoice
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9
soc/arm/nuvoton_npcx/npcx4/linker.ld
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soc/arm/nuvoton_npcx/npcx4/linker.ld
Normal file
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@ -0,0 +1,9 @@
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/* linker.ld - Linker command/script file */
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/*
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* Copyright (c) 2023 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/arch/arm/aarch32/cortex_m/scripts/linker.ld>
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soc/arm/nuvoton_npcx/npcx4/soc.c
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soc/arm/nuvoton_npcx/npcx4/soc.c
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@ -0,0 +1,21 @@
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/*
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* Copyright (c) 2023 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <soc.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
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static int soc_init(void)
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{
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return 0;
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}
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SYS_INIT(soc_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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soc/arm/nuvoton_npcx/npcx4/soc.h
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soc/arm/nuvoton_npcx/npcx4/soc.h
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@ -0,0 +1,22 @@
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/*
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* Copyright (c) 2023 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _NUVOTON_NPCX_SOC_H_
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#define _NUVOTON_NPCX_SOC_H_
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/* CMSIS required definitions */
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#define __FPU_PRESENT CONFIG_CPU_HAS_FPU
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#define __MPU_PRESENT CONFIG_CPU_HAS_ARM_MPU
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#include <reg/reg_access.h>
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#include <reg/reg_def.h>
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#include <soc_dt.h>
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#include <soc_clock.h>
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#include <soc_pins.h>
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#include <soc_power.h>
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#endif /* _NUVOTON_NPCX_SOC_H_ */
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