soc: arm: nxp: add MK22F12 definition
Add SOC definition for MK22F12 series, larger LQFP-144 K22 series parts that feature additional peripheral instances. Additionally, these parts differ from the standard MK22 in the following ways: - SYSMPU peripheral is present, so an MPU definition is required - No external oscillator divider is present This commit also updates the NXP HAL to include pin control files for these SOCs. Signed-off-by: Daniel DeGrasse <daniel@degrasse.com>
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8 changed files with 159 additions and 3 deletions
51
dts/arm/nxp/nxp_k22fx512.dtsi
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51
dts/arm/nxp/nxp_k22fx512.dtsi
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/*
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* Copyright 2023 Daniel DeGrasse
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <nxp/nxp_k2x.dtsi>
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/ {
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soc {
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i2c2: i2c@400e6000 {
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compatible = "nxp,kinetis-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x400e6000 0x1000>;
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interrupts = <74 0>;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 6>;
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status = "disabled";
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};
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spi2: spi@400ac000 {
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reg = <0x400ac000 0x88>;
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interrupts = <65 3>;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1030 12>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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uart4: uart@400ea000 {
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compatible = "nxp,kinetis-uart";
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reg = <0x400ea000 0x1000>;
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interrupts = <66 0>, <67 0>;
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interrupt-names = "status", "error";
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 10>;
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status = "disabled";
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};
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uart5: uart@400eb000 {
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compatible = "nxp,kinetis-uart";
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reg = <0x400eb000 0x1000>;
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interrupts = <68 0>, <69 0>;
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interrupt-names = "status", "error";
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 11>;
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status = "disabled";
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};
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};
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};
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@ -9,4 +9,9 @@ zephyr_sources(
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soc.c
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)
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if(DEFINED CONFIG_ARM_MPU AND DEFINED CONFIG_CPU_HAS_NXP_MPU)
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# MK22F12 series MCUs have NXP MPU
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zephyr_sources(nxp_mpu_regions.c)
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endif()
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
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@ -11,4 +11,7 @@ config SOC
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config GPIO
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default y
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config NUM_IRQS
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default 74
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endif # SOC_MK22F12
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17
soc/arm/nxp_kinetis/k2x/Kconfig.defconfig.mk22fx12
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soc/arm/nxp_kinetis/k2x/Kconfig.defconfig.mk22fx12
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# Copyright 2023 Daniel DeGrasse
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# SPDX-License-Identifier: Apache-2.0
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# Kinetis MK22FX12 configuration options
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if SOC_MK22F12
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config SOC
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default "mk22f12"
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config NUM_IRQS
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default 81
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config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
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default y
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endif # SOC_MK22F12
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@ -12,9 +12,6 @@ if SOC_SERIES_KINETIS_K2X
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config SOC_SERIES
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default "k2x"
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config NUM_IRQS
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default 74
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source "soc/arm/nxp_kinetis/k2x/Kconfig.defconfig.mk*"
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endif # SOC_SERIES_KINETIS_K2X
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@ -26,6 +26,24 @@ config SOC_MK22F51212
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select HAS_MCUX_DAC
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select HAS_MCUX_RCM
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# Note- the MK22F12 SKU is a legacy SOC, no longer officially supported by
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# NXP's MCUX SDK, and not recommended for new designs.
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config SOC_MK22F12
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bool "SOC_MK22F12"
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select HAS_MCUX
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select HAS_MCUX_SMC
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select HAS_MCUX_ADC16
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select HAS_MCUX_FTFX
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select HAS_MCUX_FTM
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select HAS_MCUX_RNGA
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select HAS_MCUX_SIM
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select HAS_OSC
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select HAS_MCG
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select CPU_HAS_FPU
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select HAS_MCUX_DAC
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select HAS_MCUX_RCM
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select CPU_HAS_NXP_MPU
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endchoice
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if SOC_SERIES_KINETIS_K2X
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@ -36,9 +54,13 @@ config SOC_PART_NUMBER_MK22FN512VLH12
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config SOC_PART_NUMBER_MK22FX512AVLK12
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bool
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config SOC_PART_NUMBER_MK22FX512VLQ12
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bool
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config SOC_PART_NUMBER_KINETIS_K2X
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string
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default "MK22FN512VLH12" if SOC_PART_NUMBER_MK22FN512VLH12
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default "MK22FX512VLQ12" if SOC_PART_NUMBER_MK22FX512VLQ12
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help
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This string holds the full part number of the SoC. It is a hidden option
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that you should not set directly. The part number selection choice defines
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59
soc/arm/nxp_kinetis/k2x/nxp_mpu_regions.c
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soc/arm/nxp_kinetis/k2x/nxp_mpu_regions.c
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/*
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* Copyright 2023 Daniel DeGrasse
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <zephyr/arch/arm/mpu/nxp_mpu.h>
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static const struct nxp_mpu_region mpu_regions[] = {
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/* Region 0 */
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/* Debugger access can't be disabled; ENET and USB devices will not be able
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* to access RAM when their regions are dynamically disabled in NXP MPU.
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*/
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MPU_REGION_ENTRY("DEBUGGER_0",
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0,
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0xFFFFFFFF,
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REGION_DEBUGGER_AND_DEVICE_ATTR),
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/* The NXP MPU does not give precedence to memory regions like the ARM
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* MPU, which means that if one region grants access then another
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* region cannot revoke access. If an application enables hardware
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* stack protection, we need to disable supervisor writes from the core
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* to the stack guard region. As a result, we cannot have a single
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* background region that enables supervisor read/write access from the
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* core to the entire address space, and instead define two background
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* regions that together cover the entire address space except for
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* SRAM.
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*/
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/* Region 1 */
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MPU_REGION_ENTRY("BACKGROUND_0",
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0,
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CONFIG_SRAM_BASE_ADDRESS-1,
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REGION_BACKGROUND_ATTR),
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/* Region 2 */
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MPU_REGION_ENTRY("BACKGROUND_1",
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CONFIG_SRAM_BASE_ADDRESS +
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(CONFIG_SRAM_SIZE * 1024),
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0xFFFFFFFF,
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REGION_BACKGROUND_ATTR),
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/* Region 3 */
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MPU_REGION_ENTRY("FLASH_0",
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CONFIG_FLASH_BASE_ADDRESS,
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(CONFIG_FLASH_BASE_ADDRESS +
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(CONFIG_FLASH_SIZE * 1024) - 1),
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REGION_FLASH_ATTR),
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/* Region 4 */
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MPU_REGION_ENTRY("RAM_U_0",
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CONFIG_SRAM_BASE_ADDRESS,
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(CONFIG_SRAM_BASE_ADDRESS +
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(CONFIG_SRAM_SIZE * 1024) - 1),
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REGION_RAM_ATTR),
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};
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const struct nxp_mpu_config mpu_config = {
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.num_regions = ARRAY_SIZE(mpu_regions),
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.mpu_regions = mpu_regions,
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.sram_region = 4,
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};
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@ -49,7 +49,9 @@ static const osc_config_t oscConfig = {
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.oscerConfig = {
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.enableMode = 0U, /* Disable external reference clock */
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#if FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER
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.erclkDiv = 0U,
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#endif
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},
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};
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