soc: intel_adsp/cavs: add arch_cpu_idle support
Cavs platforms starts from Apllolake to Raptorlake. Some of them need some workaround for arch_cpu_idle so create a bespoken one. Each workaround is configured by kconfig setting. Signed-off-by: Rander Wang <rander.wang@intel.com>
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@ -180,6 +180,51 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
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}
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#endif /* CONFIG_PM */
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#ifdef CONFIG_ARCH_CPU_IDLE_CUSTOM
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/* xt-clang removes any NOPs more than 8. So we need to set
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* no optimization to avoid those NOPs from being removed.
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*
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* This function is simply enough and full of hand written
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* assembly that optimization is not really meaningful
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* anyway. So we can skip optimization unconditionally.
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* Re-evalulate its use and add #ifdef if this assumption
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* is no longer valid.
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*/
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__no_optimization
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void arch_cpu_idle(void)
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{
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sys_trace_idle();
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/* Just spin forever with interrupts unmasked, for platforms
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* where WAITI can't be used or where its behavior is
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* complicated (Intel DSPs will power gate on idle entry under
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* some circumstances)
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*/
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if (IS_ENABLED(CONFIG_XTENSA_CPU_IDLE_SPIN)) {
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__asm__ volatile("rsil a0, 0");
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__asm__ volatile("loop_forever: j loop_forever");
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return;
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}
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/* Cribbed from SOF: workaround for a bug in some versions of
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* the LX6 IP. Preprocessor ugliness avoids the need to
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* figure out how to get the compiler to unroll a loop.
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*/
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if (IS_ENABLED(CONFIG_XTENSA_WAITI_BUG)) {
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#define NOP4 __asm__ volatile("nop; nop; nop; nop");
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#define NOP32 NOP4 NOP4 NOP4 NOP4 NOP4 NOP4 NOP4 NOP4
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#define NOP128() NOP32 NOP32 NOP32 NOP32
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NOP128();
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#undef NOP128
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#undef NOP32
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#undef NOP4
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__asm__ volatile("isync; extw");
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}
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__asm__ volatile ("waiti 0");
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}
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#endif
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__imr void power_init(void)
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{
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/* Request HP ring oscillator and
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