soc: espressif: adjust memory organization on linker
Adjust the memory organization to avoid overlapping critical regions from bootloaders (MCUboot and IDF) Signed-off-by: Almir Okato <almir.okato@espressif.com>
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4 changed files with 9 additions and 4 deletions
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@ -26,7 +26,9 @@
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#define SRAM_DRAM_START 0x3FC7C000
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#define ICACHE_SIZE 0x4000 /* ICache size is fixed to 16KB on ESP32-C3 */
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#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START)
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#define SRAM_DRAM_END 0x403D0000 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */
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/* SRAM_DRAM_END is equivalent 2nd stage bootloader iram_loader_seg
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start address (that should not be overlapped) */
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#define SRAM_DRAM_END 0x403D0000 - I_D_SRAM_OFFSET
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#define SRAM_IRAM_ORG (SRAM_IRAM_START + ICACHE_SIZE)
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#define SRAM_DRAM_ORG (SRAM_DRAM_START + ICACHE_SIZE)
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#define I_D_SRAM_SIZE SRAM_DRAM_END - SRAM_DRAM_ORG
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@ -39,13 +39,12 @@
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#define IROM_SEG_ORG 0x400D0020
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#define IROM_SEG_LEN FLASH_SIZE-0x20
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#define IROM_SEG_ALIGN 0x4
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#define IRAM_SEG_LEN 0x20000
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#else
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#define IROM_SEG_ORG 0x400D0000
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#define IROM_SEG_LEN FLASH_SIZE
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#define IROM_SEG_ALIGN 0x10000
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#define IRAM_SEG_LEN 0x13000
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#endif
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#define IRAM_SEG_LEN 0x20000
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MEMORY
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{
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@ -18,7 +18,9 @@
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#define RAM_IRAM_START 0x40020000
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#define RAM_DRAM_START 0x3ffb0000
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#define DATA_RAM_END 0x40000000
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/* DATA_RAM_END is equivalent 2nd stage bootloader iram_loader_seg
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start address (that should not be overlapped) */
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#define DATA_RAM_END 0x3FFE0000
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#define IRAM_ORG (RAM_IRAM_START + CONFIG_ESP32S2_INSTRUCTION_CACHE_SIZE \
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+ CONFIG_ESP32S2_DATA_CACHE_SIZE)
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@ -17,6 +17,8 @@
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#define SRAM_IRAM_START 0x40370000
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#define SRAM_DIRAM_I_START 0x40378000
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/* SRAM_IRAM_END is equivalent 2nd stage bootloader iram_loader_seg
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start address (that should not be overlapped) */
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#define SRAM_IRAM_END 0x403BA000
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#define I_D_SRAM_OFFSET (SRAM_DIRAM_I_START - SRAM_DRAM_START)
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