soc: Add support for RZ/T2M
This adds a new SoC: SOC_RENESAS_RZT2M and a new board: rzt2m_startek_kit Signed-off-by: Wojciech Sipak <wsipak@antmicro.com> Co-authored-by: Roman Dobrodii <rdobrodii@antmicro.com>
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6
boards/arm/rzt2m_starterkit/Kconfig.board
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6
boards/arm/rzt2m_starterkit/Kconfig.board
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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_RZT2M_STARTER_KIT
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bool "RZ/T2M Starter Kit Board"
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depends on SOC_RENESAS_RZT2M
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boards/arm/rzt2m_starterkit/Kconfig.defconfig
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boards/arm/rzt2m_starterkit/Kconfig.defconfig
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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_RZT2M_STARTER_KIT
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config BOARD
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default "rzt2m_starter_kit"
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endif
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boards/arm/rzt2m_starterkit/board.cmake
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boards/arm/rzt2m_starterkit/board.cmake
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#
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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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board_set_debugger_ifnset(jlink)
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board_set_flasher_ifnset(jlink)
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board_runner_args(jlink "--device=R9A07G075M2")
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
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95
boards/arm/rzt2m_starterkit/doc/index.rst
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boards/arm/rzt2m_starterkit/doc/index.rst
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.. _rzt2m_starterkit:
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Renesas Starter Kit+ for RZ/T2M
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===============================
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Overview
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********
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The Renesas Starter Kit+ for RZ/T2M is an evaluation and development kit for the RZ/T2M MPU.
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The board is powered through a 5V input via a DC Power Jack or USB Type-C Connector.
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.. figure:: rzt2m_starterkit.png
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:width: 800px
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:align: center
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:alt: Starter Kit+ for RZ/T2M
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Starter Kit+ for RZ/T2M (Credit: Renesas)
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Hardware
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********
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The board utilizes the SoC of part no. R9A07G075M24GBG, with 2MB of RAM.
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It has several on-board memory components:
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* SDRAM (256MBit),
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* NOR Flash (256MBit),
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* Octa Flash (512MBit),
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* HyperRAM (512Mbit),
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* QSPI Serial Flash (512Mbit),
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* I2C EEPROM (32Kbit).
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The communication interfaces include:
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* Debug interfaces (J-Link, MIPI-10, MIPI-20),
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* Ethernet,
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* CAN,
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* USB,
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* RS485,
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* UART,
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* I2C,
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* SPI.
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Supported Features
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==================
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+-----------+------------+-------------------------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+=====================================+
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| NVIC | on-chip | nested vector interrupt controller |
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+-----------+------------+-------------------------------------+
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| SYSTICK | on-chip | systick |
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+-----------+------------+-------------------------------------+
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| PINCTRL | on-chip | pinctrl |
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+-----------+------------+-------------------------------------+
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| UART | on-chip | serial |
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+-----------+------------+-------------------------------------+
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| GPIO | on-chip | gpio |
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+-----------+------------+-------------------------------------+
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Other hardware features are not currently supported by the port.
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Connections and IOs
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===================
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By default, the board is configured for use with:
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* UART0 connected to the USB serial port (pins K18, K19),
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* UART3 connected to the PMOD Header (J25, pins H16, G20),
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* LEDs defined as `led0`, `led1`, `led2` and `led3`,
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The Zephyr console uses UART0.
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Programming and Debugging
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*************************
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Debugging
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=========
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Connect to the board using the J-Link On-board USB connector.
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Use `west` to start the debug server:
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.. code-block:: console
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west debugserver
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Connect GDB to the server and load an application:
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.. code-block::
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target remote :2331
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file build/zephyr/zephyr.elf
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load
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References
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**********
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.. _RZT2M Product page: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzt2m-high-performance-multi-function-mpu-realizing-high-speed-processing-and-high-precision-control
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BIN
boards/arm/rzt2m_starterkit/doc/rzt2m_starterkit.png
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boards/arm/rzt2m_starterkit/doc/rzt2m_starterkit.png
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Binary file not shown.
After Width: | Height: | Size: 94 KiB |
17
boards/arm/rzt2m_starterkit/rzt2m_starter_kit.dts
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boards/arm/rzt2m_starterkit/rzt2m_starter_kit.dts
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/*
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* Copyright (c) 2023 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <arm/renesas/rzt2m.dtsi>
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/ {
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model = "RZT/2M Starter Kit";
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compatible = "renesas,rzt2m_starter_kit";
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chosen {
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zephyr,sram = &cpu0_atcm;
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};
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};
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boards/arm/rzt2m_starterkit/rzt2m_starter_kit.yaml
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boards/arm/rzt2m_starterkit/rzt2m_starter_kit.yaml
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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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identifier: rzt2m_starter_kit
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name: Renesas RZ/T2M Starter Kit+
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type: mcu
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arch: arm
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ram: 2048
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toolchain:
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- zephyr
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supported:
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- counter
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- uart
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- gpio
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vendor: renesas
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5
boards/arm/rzt2m_starterkit/rzt2m_starter_kit_defconfig
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boards/arm/rzt2m_starterkit/rzt2m_starter_kit_defconfig
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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SOC_RENESAS_RZT2M=y
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CONFIG_BOARD_RZT2M_STARTER_KIT=y
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dts/arm/renesas/rzt2m.dtsi
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dts/arm/renesas/rzt2m.dtsi
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/*
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* Copyright (c) 2023 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv8-r.dtsi>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "renesas,rzt2m-dev";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-r52";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-r52";
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reg = <1>;
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};
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&gic>;
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};
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soc {
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compatible = "renesas,rzt2m-soc";
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interrupt-parent = <&gic>;
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gic: interrupt-controller@94000000 {
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compatible = "arm,gic-v3", "arm,gic";
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reg = <0x94000000 0x10000>,
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<0x94100000 0x80000>;
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interrupt-controller;
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#interrupt-cells = <4>;
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status = "okay";
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};
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cpu0_atcm: memory@0 {
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compatible = "mmio-sram";
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reg = <0x00000000 DT_SIZE_K(512)>;
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};
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cpu0_btcm: memory@100000 {
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compatible = "mmio-sram";
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reg = <0x00100000 DT_SIZE_K(64)>;
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};
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sram0: memory@10000000 {
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compatible = "mmio-sram";
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reg = <0x10000000 DT_SIZE_M(2)>;
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};
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gsc: gsc@c0060000 {
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/* Global System Counter */
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compatible = "syscon";
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reg = <0xc0060000 0x30>;
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reg-io-width = <4>;
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};
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prcrn: prcrn@80281a10 {
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/* Non-safety area */
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compatible = "syscon";
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reg = <0x80281a10 0x10>;
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reg-io-width = <4>;
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};
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prcrs: prcrs@81281a00 {
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/* Safety area */
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compatible = "syscon";
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reg = <0x81281a00 0x10>;
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reg-io-width = <4>;
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};
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};
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};
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6
soc/arm/renesas_rzt2m/CMakeLists.txt
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soc/arm/renesas_rzt2m/CMakeLists.txt
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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources(
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soc.c
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)
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soc/arm/renesas_rzt2m/Kconfig
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soc/arm/renesas_rzt2m/Kconfig
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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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config SOC_RENESAS_RZT2M
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bool
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if SOC_RENESAS_RZT2M
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config SOC_PART_NUMBER_R9A07G075
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bool
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config SOC_PART_NUMBER
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default SOC_PART_NUMBER_R9A07G075
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endif # SOC_RENESAS_RZT2M
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soc/arm/renesas_rzt2m/Kconfig.defconfig
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soc/arm/renesas_rzt2m/Kconfig.defconfig
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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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if SOC_RENESAS_RZT2M
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config SOC
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default "renesas_rzt2m"
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config NUM_IRQS
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default 994
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 20000000
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config FPU
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default y
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config FLASH_SIZE
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default 0
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config FLASH_BASE_ADDRESS
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default 0
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endif # SOC_RENESAS_RZT2M
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12
soc/arm/renesas_rzt2m/Kconfig.soc
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soc/arm/renesas_rzt2m/Kconfig.soc
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# Copyright (c) 2023 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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config SOC_RENESAS_RZT2M
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bool "Renesas RZ/T2M MCU"
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select ARM
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select CPU_CORTEX_R52
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select CPU_HAS_ARM_MPU
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select GIC_V3
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select GIC_SINGLE_SECURITY_STATE
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select ARM_ARCH_TIMER
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select SYSCON
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7
soc/arm/renesas_rzt2m/linker.ld
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soc/arm/renesas_rzt2m/linker.ld
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/*
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* Copyright (c) 2023 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/arch/arm/cortex_r/scripts/linker.ld>
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76
soc/arm/renesas_rzt2m/soc.c
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soc/arm/renesas_rzt2m/soc.c
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/*
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* Copyright (c) 2023 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/init.h>
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#include <stdint.h>
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#include <zephyr/drivers/syscon.h>
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#include "soc.h"
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#include <zephyr/sys/util_macro.h>
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static const struct device *const prcrn_dev = DEVICE_DT_GET(DT_NODELABEL(prcrn));
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static const struct device *const prcrs_dev = DEVICE_DT_GET(DT_NODELABEL(prcrs));
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void rzt2m_unlock_prcrn(uint32_t mask)
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{
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uint32_t prcrn;
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syscon_read_reg(prcrn_dev, 0, &prcrn);
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prcrn |= PRC_KEY_CODE | mask;
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syscon_write_reg(prcrn_dev, 0, prcrn);
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}
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void rzt2m_lock_prcrn(uint32_t mask)
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{
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uint32_t prcrn;
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syscon_read_reg(prcrn_dev, 0, &prcrn);
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prcrn &= ~mask;
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prcrn |= PRC_KEY_CODE;
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syscon_write_reg(prcrn_dev, 0, prcrn);
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}
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void rzt2m_unlock_prcrs(uint32_t mask)
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{
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uint32_t prcrs;
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syscon_read_reg(prcrs_dev, 0, &prcrs);
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prcrs |= PRC_KEY_CODE | mask;
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syscon_write_reg(prcrs_dev, 0, prcrs);
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}
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void rzt2m_lock_prcrs(uint32_t mask)
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{
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uint32_t prcrs;
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syscon_read_reg(prcrs_dev, 0, &prcrs);
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prcrs &= ~mask;
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prcrs |= PRC_KEY_CODE;
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syscon_write_reg(prcrs_dev, 0, prcrs);
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}
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void rzt2m_enable_counters(void)
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{
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const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(gsc));
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syscon_write_reg(dev, 0, CNTCR_EN);
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}
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static int rzt2m_init(void)
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{
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/* Unlock the Protect Registers
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* so that device drivers can access configuration registers of peripherals.
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*/
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/* After the device drivers are done, lock the Protect Registers. */
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rzt2m_enable_counters();
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return 0;
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}
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SYS_INIT(rzt2m_init, PRE_KERNEL_1, 0);
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41
soc/arm/renesas_rzt2m/soc.h
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41
soc/arm/renesas_rzt2m/soc.h
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/*
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* Copyright (c) 2023 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SOC__H_
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#define _SOC__H_
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/* Do not let CMSIS to handle GIC and Timer */
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#include <stdint.h>
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#define __GIC_PRESENT 0
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#define __TIM_PRESENT 0
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/* Global system counter */
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#define CNTCR_EN BIT(0)
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#define CNTCR_HDBG BIT(1)
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/* Safety area protect register */
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#define PRCRS_CLK BIT(0)
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#define PRCRS_LPC_RESET BIT(1)
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#define PRCRS_GPIO BIT(2)
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#define PRCRS_SYS_CTRL BIT(3)
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/* Non-safety area protect register */
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#define PRCRN_PRC0 BIT(0)
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#define PRCRN_PRC1 BIT(1)
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#define PRCRN_PRC2 BIT(2)
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/* PRC Key Code - this value is required to allow any write operation
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* to the PRCRS / PRCRN registers.
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* See section 10.2 of the RZ/T2M User's Manual: Hardware.
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*/
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#define PRC_KEY_CODE 0xa500
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void rzt2m_unlock_prcrn(uint32_t mask);
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void rzt2m_lock_prcrn(uint32_t mask);
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void rzt2m_unlock_prcrs(uint32_t mask);
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void rzt2m_lock_prcrs(uint32_t mask);
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#endif /* _SOC__H_ */
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