uart: ns16550: use io-mapped DT property for IO port access
The old CONFIG_UART_NS16550_ACCESS_IOPORT has been used to indicate whether to access the NS16550 UART via IO port before device tree is used to describe hardware. Now we have device tree, and we can specify whether a particular UART needs to be accessed via IO port using property io-mapped. Therefore, CONFIG_UART_NS16550_ACCESS_IOPORT is no longer needed (and thus also CONFIG_UART_NS16550_SIMULT_ACCESS). Remove these two kconfigs and modify code to use device tree to figure out how to access the UART hardware. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
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15 changed files with 45 additions and 68 deletions
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@ -11,7 +11,10 @@
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#include <soc.h>
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#ifdef CONFIG_UART_NS16550_ACCESS_IOPORT
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#define UART_IS_IOPORT_ACCESS \
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DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_console), io_mapped)
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#if UART_IS_IOPORT_ACCESS
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/* Legacy I/O Port Access to a NS16550 UART */
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#define IN(reg) sys_in8(reg + DT_REG_ADDR(DT_CHOSEN(zephyr_console)))
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#define OUT(reg, val) sys_out8(val, reg + DT_REG_ADDR(DT_CHOSEN(zephyr_console)))
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@ -86,7 +89,7 @@ int arch_printk_char_out(int c)
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void z_x86_early_serial_init(void)
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{
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#if defined(DEVICE_MMIO_IS_IN_RAM) && !defined(CONFIG_UART_NS16550_ACCESS_IOPORT)
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#if defined(DEVICE_MMIO_IS_IN_RAM) && !UART_IS_IOPORT_ACCESS
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#ifdef X86_SOC_EARLY_SERIAL_PCIDEV
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struct pcie_bar mbar;
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pcie_get_mbar(X86_SOC_EARLY_SERIAL_PCIDEV, 0, &mbar);
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@ -44,10 +44,3 @@ endif # SHELL
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endif # ACPI
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endif # BOARD_INTEL_ADL_CRB || BOARD_INTEL_ADL_RVP
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if BOARD_INTEL_ADL_RVP
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config UART_NS16550_ACCESS_IOPORT
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default y if UART_NS16550
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endif # BOARD_INTEL_ADL_RVP
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@ -81,9 +81,6 @@ config QEMU_ICOUNT
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config QEMU_ICOUNT_SHIFT
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default 5
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config UART_NS16550_ACCESS_IOPORT
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default y if UART_NS16550
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endif # BOARD_QEMU_X86_LAKEMONT
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if BOARD_QEMU_X86_TINY
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@ -40,6 +40,7 @@
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uart0: uart@3f8 {
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compatible = "ns16550";
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reg = <0x000003f8 0x100>;
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io-mapped;
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clock-frequency = <1843200>;
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interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
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interrupt-parent = <&intc>;
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@ -60,18 +60,6 @@ config UART_NS16550_ACCESS_WORD_ONLY
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16550 (DesignWare UART) only allows word access, byte access will raise
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exception.
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config UART_NS16550_ACCESS_IOPORT
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bool
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help
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When enabled, NS16550 will not be a memory mapped device. This option
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must be selected at SoC/board level if needed.
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config UART_NS16550_SIMULT_ACCESS
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bool
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help
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When enabled, NS16550 supports IO, MMIO, PCIe UART devices simultaneously.
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For io-mapped instances, io-mapped DTS property need to be added in dtsi.
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config UART_NS16550_PARENT_INIT_LEVEL
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bool "Boot level based on parent node"
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default y if ACPI
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@ -58,6 +58,21 @@ BUILD_ASSERT(IS_ENABLED(CONFIG_PCIE), "NS16550(s) in DT need CONFIG_PCIE");
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#include <zephyr/drivers/reset.h>
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#endif
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/* If any node has property io-mapped set, we need to support IO port
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* access in the code and device config struct.
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*
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* Note that DT_ANY_INST_HAS_PROP_STATUS_OKAY() always returns true
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* as io-mapped property is considered always exists and present,
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* even if its value is zero. Therefore we cannot use it, and has to
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* resort to the follow helper to see if any okay nodes have io-mapped
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* as 1.
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*/
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#define UART_NS16550_DT_PROP_IOMAPPED_HELPER(inst, prop, def) \
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DT_INST_PROP_OR(inst, prop, def) ||
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#define UART_NS16550_IOPORT_ENABLED \
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(DT_INST_FOREACH_STATUS_OKAY_VARGS(UART_NS16550_DT_PROP_IOMAPPED_HELPER, io_mapped, 0) 0)
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/* register definitions */
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#define REG_THR 0x00 /* Transmitter holding reg. */
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@ -249,7 +264,7 @@ struct uart_ns16550_device_config {
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#if defined(CONFIG_PINCTRL)
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const struct pinctrl_dev_config *pincfg;
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#endif
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#if defined(CONFIG_UART_NS16550_ACCESS_IOPORT) || defined(CONFIG_UART_NS16550_SIMULT_ACCESS)
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#if UART_NS16550_IOPORT_ENABLED
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bool io_map;
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#endif
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#if UART_NS16550_RESET_ENABLED
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@ -282,7 +297,7 @@ struct uart_ns16550_dev_data {
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static void ns16550_outbyte(const struct uart_ns16550_device_config *cfg,
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uintptr_t port, uint8_t val)
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{
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#if defined(CONFIG_UART_NS16550_ACCESS_IOPORT) || defined(CONFIG_UART_NS16550_SIMULT_ACCESS)
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#if UART_NS16550_IOPORT_ENABLED
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if (cfg->io_map) {
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if (IS_ENABLED(CONFIG_UART_NS16550_ACCESS_WORD_ONLY)) {
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sys_out32(val, port);
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@ -305,7 +320,7 @@ static void ns16550_outbyte(const struct uart_ns16550_device_config *cfg,
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static uint8_t ns16550_inbyte(const struct uart_ns16550_device_config *cfg,
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uintptr_t port)
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{
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#if defined(CONFIG_UART_NS16550_ACCESS_IOPORT) || defined(CONFIG_UART_NS16550_SIMULT_ACCESS)
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#if UART_NS16550_IOPORT_ENABLED
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if (cfg->io_map) {
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if (IS_ENABLED(CONFIG_UART_NS16550_ACCESS_WORD_ONLY)) {
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return sys_in32(port);
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@ -330,7 +345,7 @@ static uint8_t ns16550_inbyte(const struct uart_ns16550_device_config *cfg,
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static void ns16550_outword(const struct uart_ns16550_device_config *cfg,
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uintptr_t port, uint32_t val)
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{
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#if defined(CONFIG_UART_NS16550_ACCESS_IOPORT) || defined(CONFIG_UART_NS16550_SIMULT_ACCESS)
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#if UART_NS16550_IOPORT_ENABLED
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if (cfg->io_map) {
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sys_out32(val, port);
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} else {
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static uint32_t ns16550_inword(const struct uart_ns16550_device_config *cfg,
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uintptr_t port)
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{
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#if defined(CONFIG_UART_NS16550_ACCESS_IOPORT) || defined(CONFIG_UART_NS16550_SIMULT_ACCESS)
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#if UART_NS16550_IOPORT_ENABLED
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if (cfg->io_map) {
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return sys_in32(port);
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}
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@ -365,7 +380,7 @@ static inline uint8_t reg_interval(const struct device *dev)
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static inline uintptr_t get_port(const struct device *dev)
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{
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uintptr_t port;
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#if defined(CONFIG_UART_NS16550_ACCESS_IOPORT) || defined(CONFIG_UART_NS16550_SIMULT_ACCESS)
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#if UART_NS16550_IOPORT_ENABLED
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const struct uart_ns16550_device_config *config = dev->config;
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if (config->io_map) {
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@ -658,7 +673,7 @@ static int uart_ns16550_init(const struct device *dev)
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} else
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#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(pcie) */
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{
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#if defined(CONFIG_UART_NS16550_ACCESS_IOPORT) || defined(CONFIG_UART_NS16550_SIMULT_ACCESS)
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#if UART_NS16550_IOPORT_ENABLED
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/* Map directly from DTS */
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if (!dev_cfg->io_map) {
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#else
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@ -1257,30 +1272,6 @@ static const struct uart_driver_api uart_ns16550_driver_api = {
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pcie_irq_enable(dev_cfg->pcie->bdf, irq); \
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}
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#ifdef CONFIG_UART_NS16550_ACCESS_IOPORT
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#define REG_INIT(n) \
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.port = DT_INST_REG_ADDR(n), \
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.io_map = true,
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#else
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#define REG_INIT_PCIE1(n)
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#define REG_INIT_PCIE0(n) DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)),
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#define DEV_REG_PORT_IO_1(n) \
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.port = DT_INST_REG_ADDR(n),
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#define DEV_REG_PORT_IO_0(n) \
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_CONCAT(REG_INIT_PCIE, DT_INST_ON_BUS(n, pcie))(n)
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#ifdef CONFIG_UART_NS16550_SIMULT_ACCESS
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#define DEV_IO_INIT(n) \
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.io_map = DT_INST_PROP(n, io_mapped),
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#else
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#define DEV_IO_INIT(n)
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#endif
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#define REG_INIT(n) \
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_CONCAT(DEV_REG_PORT_IO_, DT_INST_PROP(n, io_mapped))(n) \
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DEV_IO_INIT(n)
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#endif
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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#define DEV_CONFIG_IRQ_FUNC_INIT(n) \
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.irq_config_func = irq_config_func##n,
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IF_ENABLED(DT_INST_NODE_HAS_PROP(n, pinctrl_0), \
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(PINCTRL_DT_INST_DEFINE(n))); \
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static const struct uart_ns16550_device_config uart_ns16550_dev_cfg_##n = { \
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REG_INIT(n) \
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COND_CODE_0(DT_INST_ON_BUS(n, pcie), \
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(COND_CODE_1(DT_INST_PROP_OR(n, io_mapped, 0), \
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(.port = DT_INST_REG_ADDR(n),), \
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(DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)),))), \
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()) \
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IF_ENABLED(DT_INST_PROP_OR(n, io_mapped, 0), \
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(.io_map = true,)) \
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COND_CODE_1(DT_INST_NODE_HAS_PROP(n, clock_frequency), ( \
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.sys_clk_freq = DT_INST_PROP(n, clock_frequency), \
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.clock_dev = NULL, \
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@ -76,6 +76,7 @@
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compatible = "ns16550";
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clock-frequency = <16000000>;
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reg = <0x80014000 0x100>;
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io-mapped;
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interrupts = <86 0>;
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interrupt-parent = <&intc>;
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dlf = <0x01>;
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compatible = "ns16550";
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clock-frequency = <16000000>;
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reg = <0x80014100 0x100>;
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io-mapped;
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interrupts = <87 0>;
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interrupt-parent = <&intc>;
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reg-shift = <2>;
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compatible = "ns16550";
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clock-frequency = <16000000>;
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reg = <0x80014200 0x1000>;
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io-mapped;
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interrupts = <88 0>;
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interrupt-parent = <&intc>;
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reg-shift = <2>;
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compatible = "ns16550";
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clock-frequency = <144000000>;
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reg = <0x80014300 0x100>;
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io-mapped;
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interrupts = <89 0>;
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interrupt-parent = <&intc>;
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reg-shift = <2>;
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@ -239,6 +239,7 @@
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uart0_legacy: uart@3f8 {
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compatible = "ns16550";
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reg = <0x000003f8 0x100>;
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io-mapped;
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clock-frequency = <1843200>;
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interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
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interrupt-parent = <&intc>;
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uart0: uart@3f8 {
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compatible = "ns16550";
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reg = <0x000003f8 0x100>;
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io-mapped;
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clock-frequency = <1843200>;
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interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
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interrupt-parent = <&intc>;
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uart1: uart@2f8 {
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compatible = "ns16550";
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reg = <0x000002f8 0x100>;
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io-mapped;
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clock-frequency = <1843200>;
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interrupts = <3 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
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interrupt-parent = <&intc>;
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@ -51,6 +51,7 @@
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uart0: uart@3f8 {
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compatible = "ns16550";
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reg = <0x000003f8 0x100>;
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io-mapped;
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clock-frequency = <1843200>;
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interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
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interrupt-parent = <&intc>;
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uart1: uart@2f8 {
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compatible = "ns16550";
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reg = <0x000002f8 0x100>;
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io-mapped;
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clock-frequency = <1843200>;
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interrupts = <3 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
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interrupt-parent = <&intc>;
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@ -373,6 +373,7 @@
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uart_ec_0: uart@3f8 {
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compatible = "ns16550";
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reg = <0x000003f8 0x100>;
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io-mapped;
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clock-frequency = <1843200>;
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interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
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interrupt-parent = <&intc>;
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@ -34,7 +34,4 @@ config HARVARD
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config ARC_FIRQ
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default y
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config UART_NS16550_ACCESS_IOPORT
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default y
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endif # ARC_IOT
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@ -11,7 +11,4 @@ config SOC
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 25000000 if HPET_TIMER
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config UART_NS16550_ACCESS_IOPORT
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default y if UART_NS16550
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endif
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@ -11,7 +11,4 @@ config SOC
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 25000000 if HPET_TIMER
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config UART_NS16550_ACCESS_IOPORT
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default y if UART_NS16550
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endif
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@ -15,7 +15,4 @@ config X86_DYNAMIC_IRQ_STUBS
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default 16
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depends on DYNAMIC_INTERRUPTS
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config UART_NS16550_SIMULT_ACCESS
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default y if UART_NS16550
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endif # SOC_RAPTOR_LAKE
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