dai: intel: dmic: Separate fir configuration code into function
All fir filters have an identical set of registers so their definitions were combined to simplify the code. From the dai_dmic_set_config_nhlt function, a duplicate piece of code responsible for configuring fir was separated into a new function. Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
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4 changed files with 70 additions and 160 deletions
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@ -522,29 +522,16 @@ static void dai_dmic_gain_ramp(struct dai_intel_dmic *dmic)
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CIC_CONTROL_MIC_MUTE, 0);
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if (dmic->startcount == DMIC_UNMUTE_FIR) {
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switch (dmic->dai_config_params.dai_index) {
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case 0:
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dai_dmic_update_bits(dmic, dmic_base[i] + FIR_CONTROL_A,
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FIR_CONTROL_MUTE, 0);
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break;
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case 1:
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dai_dmic_update_bits(dmic, dmic_base[i] + FIR_CONTROL_B,
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FIR_CONTROL_MUTE, 0);
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break;
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}
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}
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switch (dmic->dai_config_params.dai_index) {
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case 0:
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val = FIELD_PREP(OUT_GAIN, gval);
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dai_dmic_write(dmic, dmic_base[i] + OUT_GAIN_LEFT_A, val);
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dai_dmic_write(dmic, dmic_base[i] + OUT_GAIN_RIGHT_A, val);
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break;
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case 1:
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val = FIELD_PREP(OUT_GAIN, gval);
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dai_dmic_write(dmic, dmic_base[i] + OUT_GAIN_LEFT_B, val);
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dai_dmic_write(dmic, dmic_base[i] + OUT_GAIN_RIGHT_B, val);
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break;
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dai_dmic_update_bits(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *
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dmic->dai_config_params.dai_index + FIR_CONTROL,
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FIR_CONTROL_MUTE, 0);
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}
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val = FIELD_PREP(OUT_GAIN, gval);
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dai_dmic_write(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *
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dmic->dai_config_params.dai_index + OUT_GAIN_LEFT, val);
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dai_dmic_write(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *
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dmic->dai_config_params.dai_index + OUT_GAIN_RIGHT, val);
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}
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k_spin_unlock(&dmic->lock, key);
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@ -556,8 +543,7 @@ static void dai_dmic_start(struct dai_intel_dmic *dmic)
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int i;
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int mic_a;
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int mic_b;
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int fir_a;
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int fir_b;
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int start_fir;
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/* enable port */
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key = k_spin_lock(&dmic->lock);
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@ -585,8 +571,7 @@ static void dai_dmic_start(struct dai_intel_dmic *dmic)
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mic_a = dmic->enable[i] & 1;
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mic_b = (dmic->enable[i] & 2) >> 1;
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fir_a = (dmic->enable[i] > 0) ? 1 : 0;
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fir_b = (dmic->enable[i] > 0) ? 1 : 0;
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start_fir = dmic->enable[i] > 0;
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LOG_INF("dmic_start(), pdm%d mic_a = %u, mic_b = %u", i, mic_a, mic_b);
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/* If both microphones are needed start them simultaneously
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@ -621,18 +606,10 @@ static void dai_dmic_start(struct dai_intel_dmic *dmic)
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FIELD_PREP(MIC_CONTROL_PDM_EN_B, 1));
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}
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switch (dmic->dai_config_params.dai_index) {
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case 0:
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dai_dmic_update_bits(dmic, dmic_base[i] + FIR_CONTROL_A,
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FIR_CONTROL_START,
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FIELD_PREP(FIR_CONTROL_START, fir_a));
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break;
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case 1:
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dai_dmic_update_bits(dmic, dmic_base[i] + FIR_CONTROL_B,
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FIR_CONTROL_START,
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FIELD_PREP(FIR_CONTROL_START, fir_b));
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break;
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}
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dai_dmic_update_bits(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *
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dmic->dai_config_params.dai_index + FIR_CONTROL,
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FIR_CONTROL_START,
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FIELD_PREP(FIR_CONTROL_START, start_fir));
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}
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#ifndef CONFIG_SOC_SERIES_INTEL_ACE
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@ -694,18 +671,10 @@ static void dai_dmic_stop(struct dai_intel_dmic *dmic, bool stop_is_pause)
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CIC_CONTROL_SOFT_RESET |
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CIC_CONTROL_MIC_MUTE);
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}
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switch (dmic->dai_config_params.dai_index) {
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case 0:
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dai_dmic_update_bits(dmic, dmic_base[i] + FIR_CONTROL_A,
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FIR_CONTROL_MUTE,
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FIR_CONTROL_MUTE);
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break;
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case 1:
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dai_dmic_update_bits(dmic, dmic_base[i] + FIR_CONTROL_B,
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FIR_CONTROL_MUTE,
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FIR_CONTROL_MUTE);
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break;
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}
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dai_dmic_update_bits(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *
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dmic->dai_config_params.dai_index + FIR_CONTROL,
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FIR_CONTROL_MUTE,
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FIR_CONTROL_MUTE);
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}
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k_spin_unlock(&dmic->lock, key);
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@ -51,7 +51,7 @@ static int dai_nhlt_get_clock_div(const struct dai_intel_dmic *dmic, const int p
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p_clkdiv = FIELD_GET(MIC_CONTROL_PDM_CLKDIV, val) + 2;
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val = dai_dmic_read(dmic, base[pdm] +
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(dmic->dai_config_params.dai_index ? FIR_CONFIG_B : FIR_CONFIG_A));
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FIR_CHANNEL_REGS_SIZE * dmic->dai_config_params.dai_index + FIR_CONFIG);
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LOG_ERR("pdm = %d, FIR_CONFIG = 0x%08X", pdm, val);
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p_mfir = FIELD_GET(FIR_CONFIG_FIR_DECIMATION, val) + 1;
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@ -503,6 +503,32 @@ static void print_fir_config(const struct nhlt_pdm_ctrl_fir_cfg *fir_cfg)
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LOG_DBG("OUT_GAIN_RIGHT = %08x", fir_cfg->out_gain_right);
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}
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static void configure_fir(struct dai_intel_dmic *dmic, const uint32_t base,
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const struct nhlt_pdm_ctrl_fir_cfg *fir_cfg)
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{
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uint32_t val;
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print_fir_config(fir_cfg);
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/* Use FIR_CONFIG as such */
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val = fir_cfg->fir_config;
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dai_dmic_write(dmic, base + FIR_CONFIG, val);
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val = fir_cfg->fir_control;
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print_fir_control(val);
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/* Clear START, set MUTE */
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val = (val & ~FIR_CONTROL_START) | FIR_CONTROL_MUTE;
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dai_dmic_write(dmic, base + FIR_CONTROL, val);
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LOG_DBG("FIR_CONTROL = %08x", val);
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/* Use DC_OFFSET and GAIN as such */
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dai_dmic_write(dmic, base + DC_OFFSET_LEFT, fir_cfg->dc_offset_left);
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dai_dmic_write(dmic, base + DC_OFFSET_RIGHT, fir_cfg->dc_offset_right);
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dai_dmic_write(dmic, base + OUT_GAIN_LEFT, fir_cfg->out_gain_left);
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dai_dmic_write(dmic, base + OUT_GAIN_RIGHT, fir_cfg->out_gain_right);
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}
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int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cfg)
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{
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struct nhlt_pdm_ctrl_cfg *pdm_cfg[DMIC_HW_CONTROLLERS_MAX];
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@ -514,7 +540,6 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
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uint32_t out_control[DMIC_HW_FIFOS_MAX] = {0};
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uint32_t channel_ctrl_mask;
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uint32_t fir_control;
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uint32_t pdm_ctrl_mask;
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uint32_t val;
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const uint8_t *p = bespoke_cfg;
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@ -650,6 +675,10 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
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LOG_DBG("dmic_set_config_nhlt(): MIC_CONTROL = %08x", val);
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}
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configure_fir(dmic, base[n] +
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FIR_CHANNEL_REGS_SIZE * dmic->dai_config_params.dai_index,
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&pdm_cfg[n]->fir_config[dmic->dai_config_params.dai_index]);
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/* FIR A */
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fir_cfg_a[n] = &pdm_cfg[n]->fir_config[0];
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val = fir_cfg_a[n]->fir_config;
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@ -657,32 +686,6 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
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fir_length_a = fir_length + 1; /* Need for parsing */
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fir_decimation = FIELD_GET(FIR_CONFIG_FIR_DECIMATION, val);
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p_mfira = fir_decimation + 1;
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if (dmic->dai_config_params.dai_index == 0) {
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print_fir_config(fir_cfg_a[n]);
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/* Use FIR_CONFIG_A as such */
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dai_dmic_write(dmic, base[n] + FIR_CONFIG_A, val);
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val = fir_cfg_a[n]->fir_control;
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/* Clear START, set MUTE */
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fir_control = (val & ~FIR_CONTROL_START) | FIR_CONTROL_MUTE;
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dai_dmic_write(dmic, base[n] + FIR_CONTROL_A, fir_control);
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LOG_DBG("dmic_set_config_nhlt(): FIR_CONTROL_A = %08x", fir_control);
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/* Use DC_OFFSET and GAIN as such */
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val = fir_cfg_a[n]->dc_offset_left;
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dai_dmic_write(dmic, base[n] + DC_OFFSET_LEFT_A, val);
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val = fir_cfg_a[n]->dc_offset_right;
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dai_dmic_write(dmic, base[n] + DC_OFFSET_RIGHT_A, val);
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val = fir_cfg_a[n]->out_gain_left;
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dai_dmic_write(dmic, base[n] + OUT_GAIN_LEFT_A, val);
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val = fir_cfg_a[n]->out_gain_right;
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dai_dmic_write(dmic, base[n] + OUT_GAIN_RIGHT_A, val);
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}
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/* FIR B */
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fir_cfg_b[n] = &pdm_cfg[n]->fir_config[1];
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@ -691,32 +694,6 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf
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fir_length_b = fir_length + 1; /* Need for parsing */
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fir_decimation = FIELD_GET(FIR_CONFIG_FIR_DECIMATION, val);
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p_mfirb = fir_decimation + 1;
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if (dmic->dai_config_params.dai_index == 1) {
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print_fir_config(fir_cfg_b[n]);
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/* Use FIR_CONFIG_B as such */
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dai_dmic_write(dmic, base[n] + FIR_CONFIG_B, val);
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val = fir_cfg_b[n]->fir_control;
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/* Clear START, set MUTE */
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fir_control = (val & ~FIR_CONTROL_START) | FIR_CONTROL_MUTE;
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dai_dmic_write(dmic, base[n] + FIR_CONTROL_B, fir_control);
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LOG_DBG("dmic_set_config_nhlt(): FIR_CONTROL_B = %08x", fir_control);
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/* Use DC_OFFSET and GAIN as such */
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val = fir_cfg_b[n]->dc_offset_left;
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dai_dmic_write(dmic, base[n] + DC_OFFSET_LEFT_B, val);
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val = fir_cfg_b[n]->dc_offset_right;
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dai_dmic_write(dmic, base[n] + DC_OFFSET_RIGHT_B, val);
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val = fir_cfg_b[n]->out_gain_left;
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dai_dmic_write(dmic, base[n] + OUT_GAIN_LEFT_B, val);
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val = fir_cfg_b[n]->out_gain_right;
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dai_dmic_write(dmic, base[n] + OUT_GAIN_RIGHT_B, val);
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}
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/* Set up FIR coefficients RAM */
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val = pdm_cfg[n]->reuse_fir_from_pdm;
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@ -122,44 +122,26 @@
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/* FIR config */
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/* Control for the FIR decimator (channel A) */
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#define FIR_CONTROL_A 0x020
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/* Control for the FIR decimator */
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#define FIR_CONTROL 0x020
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/* Configuration of FIR decimator parameters (channel A) */
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#define FIR_CONFIG_A 0x024
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/* Configuration of FIR decimator parameters */
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#define FIR_CONFIG 0x024
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/* DC offset for left channel */
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#define DC_OFFSET_LEFT_A 0x028
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#define DC_OFFSET_LEFT 0x028
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/* DC offset for right channel */
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#define DC_OFFSET_RIGHT_A 0x02c
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#define DC_OFFSET_RIGHT 0x02c
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/* Gain for left channel */
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#define OUT_GAIN_LEFT_A 0x030
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#define OUT_GAIN_LEFT 0x030
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/* Gain for right channel */
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#define OUT_GAIN_RIGHT_A 0x034
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#define OUT_GAIN_RIGHT 0x034
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/* Control for the FIR decimator (channel B) */
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#define FIR_CONTROL_B 0x040
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/* Configuration of FIR decimator parameters (channel B) */
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#define FIR_CONFIG_B 0x044
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/* DC offset for left channel */
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#define DC_OFFSET_LEFT_B 0x048
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/* DC offset for right channel */
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#define DC_OFFSET_RIGHT_B 0x04c
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/* Gain for left channel */
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#define OUT_GAIN_LEFT_B 0x050
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/* Gain for right channel */
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#define OUT_GAIN_RIGHT_B 0x054
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#define PDM_COEFFICIENT_A 0x400
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#define PDM_COEFFICIENT_B 0x800
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/* Offset to secondary FIR */
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#define FIR_CHANNEL_REGS_SIZE 0x20
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/* Digital Mic Shim Registers */
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@ -119,44 +119,26 @@
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/* FIR config */
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/* Control for the FIR decimator (channel A) */
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#define FIR_CONTROL_A 0x020
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/* Control for the FIR decimator */
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#define FIR_CONTROL 0x020
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/* Configuration of FIR decimator parameters (channel A) */
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#define FIR_CONFIG_A 0x024
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/* Configuration of FIR decimator parameters */
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#define FIR_CONFIG 0x024
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/* DC offset for left channel */
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#define DC_OFFSET_LEFT_A 0x028
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#define DC_OFFSET_LEFT 0x028
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/* DC offset for right channel */
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#define DC_OFFSET_RIGHT_A 0x02c
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#define DC_OFFSET_RIGHT 0x02c
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/* Gain for left channel */
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#define OUT_GAIN_LEFT_A 0x030
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#define OUT_GAIN_LEFT 0x030
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/* Gain for right channel */
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#define OUT_GAIN_RIGHT_A 0x034
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#define OUT_GAIN_RIGHT 0x034
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/* Control for the FIR decimator (channel B) */
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#define FIR_CONTROL_B 0x040
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/* Configuration of FIR decimator parameters (channel B) */
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#define FIR_CONFIG_B 0x044
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/* DC offset for left channel */
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#define DC_OFFSET_LEFT_B 0x048
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/* DC offset for right channel */
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#define DC_OFFSET_RIGHT_B 0x04c
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/* Gain for left channel */
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#define OUT_GAIN_LEFT_B 0x050
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/* Gain for right channel */
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#define OUT_GAIN_RIGHT_B 0x054
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#define PDM_COEFFICIENT_A 0x400
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#define PDM_COEFFICIENT_B 0x800
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/* Offset to secondary FIR */
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#define FIR_CHANNEL_REGS_SIZE 0x20
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/* Digital Mic Shim Registers */
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