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drivers: pinctrl: Add pinctrl driver for Gecko Series 1

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This adds a new pinctrl driver for EFM32.

Co-authored-by: Todd Dust <Todd.Dust@silabs.com>
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
This commit is contained in:
Wojciech Sipak 2023-07-21 17:20:29 +02:00 • committed by Carles Cufí
commit 40fa96506b
10 changed files with 335 additions and 51 deletions
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19
boards/arm/efm32pg_stk3402a/efm32pg_stk3402a-pinctrl.dtsi Normal file
View file

@ -0,0 +1,19 @@
/*
* Copyright (c) 2023 Silicon Labs
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <dt-bindings/pinctrl/gecko-pinctrl-s1.h>
&pinctrl {
/* configuration for usart0 device, default state - operating as UART */
usart0_default: usart0_default {
group1 {
psels = <GECKO_PSEL(UART_TX, A, 0)>,
<GECKO_PSEL(UART_RX, A, 1)>,
<GECKO_LOC(UART_TX, 0)>,
<GECKO_LOC(UART_RX, 0)>;
};
};
};

5
boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_common.dtsi
View file

@ -5,6 +5,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "efm32pg_stk3402a-pinctrl.dtsi"
/ {
model = "Silicon Labs EFM32PG STK3402A board";
@ -67,8 +68,8 @@
&usart0 {
current-speed = <115200>;
location-rx = <GECKO_LOCATION(0) GECKO_PORT_A GECKO_PIN(1)>;
location-tx = <GECKO_LOCATION(0) GECKO_PORT_A GECKO_PIN(0)>;
pinctrl-0 = <&usart0_default>;
pinctrl-names = "default";
status = "okay";
};

227
drivers/pinctrl/pinctrl_gecko.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2022 Silicon Labs
* Copyright (c) 2023 Silicon Labs
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -11,39 +11,87 @@
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
{
USART_TypeDef *base = (USART_TypeDef *)reg;
int usart_num = USART_NUM(base);
LEUART_TypeDef *lebase = (LEUART_TypeDef *)reg;
uint8_t loc;
#ifndef CONFIG_SOC_GECKO_SERIES1
int usart_num = USART_NUM(base);
#endif
#ifdef CONFIG_SPI_GECKO
struct soc_gpio_pin spi_pin_cfg = {0, 0, 0, 0};
#endif /* CONFIG_SPI_GECKO */
#ifdef CONFIG_UART_GECKO
struct soc_gpio_pin rxpin = {0, 0, 0, 0};
struct soc_gpio_pin txpin = {0, 0, 0, 0};
#endif /* CONFIG_UART_GECKO */
struct soc_gpio_pin pin_config = {0, 0, 0, 0};
for (uint8_t i = 0U; i < pin_cnt; i++) {
pin_config.port = GECKO_GET_PORT(pins[i]);
pin_config.pin = GECKO_GET_PIN(pins[i]);
loc = GECKO_GET_LOC(pins[i]);
switch (GECKO_GET_FUN(pins[i])) {
#ifdef CONFIG_UART_GECKO
case GECKO_FUN_UART_RX:
rxpin.port = GECKO_GET_PORT(pins[i]);
rxpin.pin = GECKO_GET_PIN(pins[i]);
rxpin.mode = gpioModeInput;
rxpin.out = 1;
GPIO_PinModeSet(rxpin.port, rxpin.pin, rxpin.mode,
rxpin.out);
pin_config.mode = gpioModeInput;
pin_config.out = 1;
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
break;
case GECKO_FUN_UART_TX:
txpin.port = GECKO_GET_PORT(pins[i]);
txpin.pin = GECKO_GET_PIN(pins[i]);
txpin.mode = gpioModePushPull;
txpin.out = 1;
GPIO_PinModeSet(txpin.port, txpin.pin, txpin.mode,
txpin.out);
pin_config.mode = gpioModePushPull;
pin_config.out = 1;
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
break;
#ifdef CONFIG_SOC_GECKO_SERIES1
case GECKO_FUN_UART_RTS:
pin_config.mode = gpioModePushPull;
pin_config.out = 1;
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
break;
case GECKO_FUN_UART_CTS:
pin_config.mode = gpioModeInput;
pin_config.out = 1;
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
break;
case GECKO_FUN_UART_RX_LOC:
base->ROUTEPEN |= USART_ROUTEPEN_RXPEN;
base->ROUTELOC0 &= ~_USART_ROUTELOC0_RXLOC_MASK;
base->ROUTELOC0 |= (loc << _USART_ROUTELOC0_RXLOC_SHIFT);
break;
case GECKO_FUN_UART_TX_LOC:
base->ROUTEPEN |= USART_ROUTEPEN_TXPEN;
base->ROUTELOC0 &= ~_USART_ROUTELOC0_TXLOC_MASK;
base->ROUTELOC0 |= (loc << _USART_ROUTELOC0_TXLOC_SHIFT);
break;
case GECKO_FUN_UART_RTS_LOC:
base->ROUTEPEN |= USART_ROUTEPEN_RTSPEN;
base->ROUTELOC1 &= ~_USART_ROUTELOC1_RTSLOC_MASK;
base->ROUTELOC1 |= (loc << _USART_ROUTELOC1_RTSLOC_SHIFT);
break;
case GECKO_FUN_UART_CTS_LOC:
base->ROUTEPEN |= USART_ROUTEPEN_CTSPEN;
base->ROUTELOC1 &= ~_USART_ROUTELOC1_CTSLOC_MASK;
base->ROUTELOC1 |= (loc << _USART_ROUTELOC1_CTSLOC_SHIFT);
break;
case GECKO_FUN_LEUART_RX_LOC:
lebase->ROUTEPEN |= LEUART_ROUTEPEN_RXPEN;
lebase->ROUTELOC0 &= ~_LEUART_ROUTELOC0_RXLOC_MASK;
lebase->ROUTELOC0 |= (loc << _LEUART_ROUTELOC0_RXLOC_SHIFT);
break;
case GECKO_FUN_LEUART_TX_LOC:
lebase->ROUTEPEN |= LEUART_ROUTEPEN_TXPEN;
lebase->ROUTELOC0 &= ~_LEUART_ROUTELOC0_TXLOC_MASK;
lebase->ROUTELOC0 |= (loc << _LEUART_ROUTELOC0_TXLOC_SHIFT);
break;
#else /* CONFIG_SOC_GECKO_SERIES1 */
case GECKO_FUN_UART_LOC:
loc = GECKO_GET_LOC(pins[i]);
#ifdef CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
/* For SOCs with configurable pin_cfg locations (set in SOC Kconfig) */
base->ROUTEPEN = USART_ROUTEPEN_RXPEN | USART_ROUTEPEN_TXPEN;
@ -57,11 +105,11 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp
GPIO->USARTROUTE[usart_num].ROUTEEN =
GPIO_USART_ROUTEEN_TXPEN | GPIO_USART_ROUTEEN_RXPEN;
GPIO->USARTROUTE[usart_num].TXROUTE =
(txpin.pin << _GPIO_USART_TXROUTE_PIN_SHIFT) |
(txpin.port << _GPIO_USART_TXROUTE_PORT_SHIFT);
(pin_config.pin << _GPIO_USART_TXROUTE_PIN_SHIFT) |
(pin_config.port << _GPIO_USART_TXROUTE_PORT_SHIFT);
GPIO->USARTROUTE[usart_num].RXROUTE =
(rxpin.pin << _GPIO_USART_RXROUTE_PIN_SHIFT) |
(rxpin.port << _GPIO_USART_RXROUTE_PORT_SHIFT);
(pin_config.pin << _GPIO_USART_RXROUTE_PIN_SHIFT) |
(pin_config.port << _GPIO_USART_RXROUTE_PORT_SHIFT);
#endif /* CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION */
#ifdef UART_GECKO_HW_FLOW_CONTROL
@ -98,47 +146,128 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp
}
#endif /* UART_GECKO_HW_FLOW_CONTROL */
break;
#endif /* CONFIG_SOC_GECKO_SERIES1 */
#endif /* CONFIG_UART_GECKO */
#ifdef CONFIG_SPI_GECKO
#ifdef CONFIG_SOC_GECKO_SERIES1
case GECKO_FUN_SPIM_SCK:
pin_config.mode = gpioModePushPull;
pin_config.out = 1;
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
break;
case GECKO_FUN_SPIM_MOSI:
pin_config.mode = gpioModePushPull;
pin_config.out = 1;
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
break;
case GECKO_FUN_SPIM_MISO:
pin_config.mode = gpioModeInput;
pin_config.out = 1;
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
break;
case GECKO_FUN_SPIM_CS:
pin_config.mode = gpioModePushPull;
pin_config.out = 1;
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
break;
case GECKO_FUN_SPIS_SCK:
pin_config.mode = gpioModeInput;
pin_config.out = 1;
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
break;
case GECKO_FUN_SPIS_MOSI:
pin_config.mode = gpioModeInput;
pin_config.out = 1;
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
break;
case GECKO_FUN_SPIS_MISO:
pin_config.mode = gpioModePushPull;
pin_config.out = 1;
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
break;
case GECKO_FUN_SPIS_CS:
pin_config.mode = gpioModeInput;
pin_config.out = 1;
GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode,
pin_config.out);
break;
case GECKO_FUN_SPI_SCK_LOC:
base->ROUTEPEN |= USART_ROUTEPEN_CLKPEN;
base->ROUTELOC0 &= ~_USART_ROUTELOC0_CLKLOC_MASK;
base->ROUTELOC0 |= (loc << _USART_ROUTELOC0_CLKLOC_SHIFT);
break;
case GECKO_FUN_SPI_MOSI_LOC:
base->ROUTEPEN |= USART_ROUTEPEN_TXPEN;
base->ROUTELOC0 &= ~_USART_ROUTELOC0_TXLOC_MASK;
base->ROUTELOC0 |= (loc << _USART_ROUTELOC0_TXLOC_SHIFT);
break;
case GECKO_FUN_SPI_MISO_LOC:
base->ROUTEPEN |= USART_ROUTEPEN_RXPEN;
base->ROUTELOC0 &= ~_USART_ROUTELOC0_RXLOC_MASK;
base->ROUTELOC0 |= (loc << _USART_ROUTELOC0_RXLOC_SHIFT);
break;
case GECKO_FUN_SPI_CS_LOC:
base->ROUTEPEN |= USART_ROUTEPEN_CSPEN;
base->ROUTELOC0 &= ~_USART_ROUTELOC0_CSLOC_MASK;
base->ROUTELOC0 |= (loc << _USART_ROUTELOC0_CSLOC_SHIFT);
break;
#else /* CONFIG_SOC_GECKO_SERIES1 */
case GECKO_FUN_SPI_SCK:
spi_pin_cfg.port = GECKO_GET_PORT(pins[i]);
spi_pin_cfg.pin = GECKO_GET_PIN(pins[i]);
spi_pin_cfg.mode = gpioModePushPull;
spi_pin_cfg.out = 1;
pin_config.mode = gpioModePushPull;
pin_config.out = 1;
GPIO->USARTROUTE[usart_num].ROUTEEN |= GPIO_USART_ROUTEEN_CLKPEN;
GPIO->USARTROUTE[usart_num].CLKROUTE =
(spi_pin_cfg.pin << _GPIO_USART_CLKROUTE_PIN_SHIFT) |
(spi_pin_cfg.port << _GPIO_USART_CLKROUTE_PORT_SHIFT);
(pin_config.pin << _GPIO_USART_CLKROUTE_PIN_SHIFT) |
(pin_config.port << _GPIO_USART_CLKROUTE_PORT_SHIFT);
break;
case GECKO_FUN_SPI_MOSI:
spi_pin_cfg.port = GECKO_GET_PORT(pins[i]);
spi_pin_cfg.pin = GECKO_GET_PIN(pins[i]);
spi_pin_cfg.mode = gpioModePushPull;
spi_pin_cfg.out = 1;
pin_config.mode = gpioModePushPull;
pin_config.out = 1;
GPIO->USARTROUTE[usart_num].ROUTEEN |= GPIO_USART_ROUTEEN_TXPEN;
GPIO->USARTROUTE[usart_num].TXROUTE =
(spi_pin_cfg.pin << _GPIO_USART_TXROUTE_PIN_SHIFT) |
(spi_pin_cfg.port << _GPIO_USART_TXROUTE_PORT_SHIFT);
(pin_config.pin << _GPIO_USART_TXROUTE_PIN_SHIFT) |
(pin_config.port << _GPIO_USART_TXROUTE_PORT_SHIFT);
break;
case GECKO_FUN_SPI_MISO:
spi_pin_cfg.port = GECKO_GET_PORT(pins[i]);
spi_pin_cfg.pin = GECKO_GET_PIN(pins[i]);
spi_pin_cfg.mode = gpioModeInput;
spi_pin_cfg.out = 1;
pin_config.mode = gpioModeInput;
pin_config.out = 1;
GPIO->USARTROUTE[usart_num].ROUTEEN |= GPIO_USART_ROUTEEN_RXPEN;
GPIO->USARTROUTE[usart_num].RXROUTE =
(spi_pin_cfg.pin << _GPIO_USART_RXROUTE_PIN_SHIFT) |
(spi_pin_cfg.port << _GPIO_USART_RXROUTE_PORT_SHIFT);
(pin_config.pin << _GPIO_USART_RXROUTE_PIN_SHIFT) |
(pin_config.port << _GPIO_USART_RXROUTE_PORT_SHIFT);
break;
#endif /* CONFIG_SOC_GECKO_SERIES1 */
#endif /* CONFIG_SPI_GECKO */
default:
return -ENOTSUP;
}
#ifdef CONFIG_SPI_GECKO
GPIO_PinModeSet(spi_pin_cfg.port, spi_pin_cfg.pin,
spi_pin_cfg.mode, spi_pin_cfg.out);
#endif /* CONFIG_SPI_GECKO */
#if defined(CONFIG_SPI_GECKO) && !defined(CONFIG_SOC_GECKO_SERIES1)
GPIO_PinModeSet(pin_config.port, pin_config.pin,
pin_config.mode, pin_config.out);
#endif /* defined(CONFIG_SPI_GECKO) && !defined(CONFIG_SOC_GECKO_SERIES1) */
}
return 0;

1
drivers/serial/Kconfig.gecko
View file

@ -10,5 +10,6 @@ config UART_GECKO
select SERIAL_HAS_DRIVER
select SERIAL_SUPPORT_INTERRUPT
select SOC_GECKO_USART
select PINCTRL if SOC_GECKO_SERIES1
help
Enable the Gecko uart driver.

8
dts/arm/silabs/efm32_jg_pg_12b.dtsi
View file

@ -253,6 +253,14 @@
status = "disabled";
#io-channel-cells = <1>;
};
pinctrl: pin-controller {
/* Pin controller is a "virtual" device since SiLabs SoCs do pin
* control in a distributed way (GPIO registers and PSEL
* registers on each peripheral).
*/
compatible = "silabs,gecko-pinctrl";
};
};
};

113
include/zephyr/dt-bindings/pinctrl/gecko-pinctrl-s1.h Normal file
View file

@ -0,0 +1,113 @@
/*
* Copyright (c) 2023 Silicon Labs
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_GECKO_PINCTRL_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_GECKO_PINCTRL_H_
/*
* The whole GECKO_pin configuration information is encoded in a 32-bit bitfield
* organized as follows:
*
* - 31..24: Pin function.
* - 23..16: Reserved.
* - 15..8: Port for UART_RX/UART_TX functions.
* - 7..0: Pin number for UART_RX/UART_TX functions.
* - 15..8: Reserved for UART_LOC function.
* - 7..0: Loc for UART_LOC function.
*/
/**
* @name GECKO_pin configuration bit field positions and masks.
* @{
*/
/** Position of the function field. */
#define GECKO_FUN_POS 24U
/** Mask for the function field. */
#define GECKO_FUN_MSK 0xFFFU
/** Position of the pin field. */
#define GECKO_PIN_POS 0U
/** Mask for the pin field. */
#define GECKO_PIN_MSK 0xFFU
/** Position of the port field. */
#define GECKO_PORT_POS 8U
/** Mask for the port field. */
#define GECKO_PORT_MSK 0xFFU
/** Position of the loc field. */
#define GECKO_LOC_POS 0U
/** Mask for the pin field. */
#define GECKO_LOC_MSK 0xFFU
/** @} */
/**
* @name GECKO_pinctrl pin functions.
* @{
*/
/** UART TX */
#define GECKO_FUN_UART_TX 0U
/** UART RX */
#define GECKO_FUN_UART_RX 1U
/** UART RTS */
#define GECKO_FUN_UART_RTS 2U
/** UART CTS */
#define GECKO_FUN_UART_CTS 3U
/** UART RX LOCATION */
#define GECKO_FUN_UART_RX_LOC 4U
/** UART TX LOCATION */
#define GECKO_FUN_UART_TX_LOC 5U
/** UART RTS LOCATION */
#define GECKO_FUN_UART_RTS_LOC 6U
/** UART CTS LOCATION */
#define GECKO_FUN_UART_CTS_LOC 7U
#define GECKO_FUN_SPIM_MISO 8U
#define GECKO_FUN_SPIM_MOSI 9U
#define GECKO_FUN_SPIM_CS 10U
#define GECKO_FUN_SPIM_SCK 11U
#define GECKO_FUN_LEUART_RX_LOC 12U
#define GECKO_FUN_LEUART_TX_LOC 13U
#define GECKO_FUN_SPIS_MISO 14U
#define GECKO_FUN_SPIS_MOSI 15U
#define GECKO_FUN_SPIS_CS 16U
#define GECKO_FUN_SPIS_SCK 17U
#define GECKO_FUN_SPI_MISO_LOC 18U
#define GECKO_FUN_SPI_MOSI_LOC 19U
#define GECKO_FUN_SPI_CS_LOC 20U
#define GECKO_FUN_SPI_SCK_LOC 21U
/** @} */
/**
* @brief Utility macro to build GECKO psels property entry.
*
* @param fun Pin function configuration (see GECKO_FUNC_{name} macros).
* @param port Port (0 or 1).
* @param pin Pin (0..31).
*/
#define GECKO_PSEL(fun, port, pin) \
(((GECKO_PORT_##port & GECKO_PORT_MSK) << GECKO_PORT_POS) | \
((GECKO_PIN(##pin##) & GECKO_PIN_MSK) << GECKO_PIN_POS) | \
((GECKO_FUN_##fun & GECKO_FUN_MSK) << GECKO_FUN_POS))
/**
* @brief Utility macro to build GECKO_psels property entry.
*
* @param fun Pin function configuration (see GECKO_FUNC_{name} macros).
* @param loc Location.
*/
#define GECKO_LOC(fun, loc) \
(((GECKO_LOCATION(##loc##) & GECKO_LOC_MSK) << GECKO_LOC_POS) | \
((GECKO_FUN_##fun##_LOC & GECKO_FUN_MSK) << GECKO_FUN_POS))
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_GECKO_PINCTRL_H_ */

7
soc/arm/silabs_exx32/Kconfig
View file

@ -28,6 +28,13 @@ config SOC_GECKO_SERIES2
This is equivalent of _SILICON_LABS_32B_SERIES_2 definition in HAL
code.
config SOC_GECKO_SERIES1
bool
help
Set if we're building for Gecko Series 1 SoC.
This is equivalent of _SILICON_LABS_32B_SERIES_1 definition in HAL
code.
config SOC_GECKO_BURTC
bool
help

4
soc/arm/silabs_exx32/common/pinctrl_soc.h
View file

@ -15,7 +15,11 @@
#include <stdint.h>
#include <zephyr/devicetree.h>
#if CONFIG_SOC_GECKO_SERIES1
#include <zephyr/dt-bindings/pinctrl/gecko-pinctrl-s1.h>
#else
#include <zephyr/dt-bindings/pinctrl/gecko-pinctrl.h>
#endif
#ifdef __cplusplus
extern "C" {

1
soc/arm/silabs_exx32/efm32jg12b/Kconfig.series
View file

@ -13,6 +13,7 @@ config SOC_SERIES_EFM32JG12B
select SOC_FAMILY_EXX32
select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
select SOC_GECKO_HAS_HFRCO_FREQRANGE
select SOC_GECKO_SERIES1
select SOC_GECKO_CMU
select SOC_GECKO_EMU
select SOC_GECKO_GPIO

1
soc/arm/silabs_exx32/efm32pg12b/Kconfig.series
View file

@ -13,6 +13,7 @@ config SOC_SERIES_EFM32PG12B
select CPU_HAS_FPU
select CPU_HAS_ARM_MPU
select SOC_FAMILY_EXX32
select SOC_GECKO_SERIES1
select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
select SOC_GECKO_HAS_HFRCO_FREQRANGE
select SOC_GECKO_CMU