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intel_adsp: ace: Restore IDC interrupt on D3 exit

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After exiting D3 state if IMR context save is enabled, IDC interrupt
must be re-enabled again for all cores.

Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
This commit is contained in:
Serhiy Katsyuba 2023-06-27 12:55:22 +02:00 • committed by Fabio Baltieri
commit 431108d89e
2 changed files with 20 additions and 0 deletions
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11
soc/xtensa/intel_adsp/ace/multiprocessing.c
View file

@ -79,6 +79,17 @@ void soc_mp_init(void)
soc_cpus_active[0] = true;
}
#ifdef CONFIG_ADSP_IMR_CONTEXT_SAVE
/*
* Called after exiting D3 state when context restore is enabled.
* Re-enables IDC interrupt again for all cores. Called once from core 0.
*/
void soc_mp_on_d3_exit(void)
{
soc_mp_init();
}
#endif
void soc_start_core(int cpu_num)
{
int retry = CORE_POWER_CHECK_NUM;

9
soc/xtensa/intel_adsp/ace/power.c
View file

@ -75,6 +75,14 @@ uint8_t *global_imr_ram_storage;
* @biref a d3 restore boot entry point
*/
extern void boot_entry_d3_restore(void);
/*
* @brief re-enables IDC interrupt for all cores after exiting D3 state
*
* Called once from core 0
*/
extern void soc_mp_on_d3_exit(void);
#else
/*
@ -321,6 +329,7 @@ __weak void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
imr_layout->imr_state.header.imr_ram_storage = NULL;
sys_clock_idle_exit();
mem_window_idle_exit();
soc_mp_on_d3_exit();
}
#endif /* CONFIG_ADSP_IMR_CONTEXT_SAVE */
soc_cpus_active[cpu] = true;