xtensa: rename z_xtensa_irq to simple xtensa_irq
This gets rid of the z_ prefix. Note that z_xt_*() are being used by the HAL so they cannot be renamed. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
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8bf20ee975
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6d5e0c25a6
8 changed files with 51 additions and 26 deletions
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@ -972,8 +972,7 @@ void arch_gdb_init(void)
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* after level-1 interrupts is for level-2 interrupt.
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* So need to do an offset by subtraction.
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*/
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z_xtensa_irq_enable(XCHAL_NUM_EXTINTERRUPTS +
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XCHAL_DEBUGLEVEL - 2);
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xtensa_irq_enable(XCHAL_NUM_EXTINTERRUPTS + XCHAL_DEBUGLEVEL - 2);
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/*
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* Break and go into the GDB stub.
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@ -75,7 +75,7 @@ void z_irq_spurious(const void *arg)
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z_xtensa_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
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}
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int z_xtensa_irq_is_enabled(unsigned int irq)
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int xtensa_irq_is_enabled(unsigned int irq)
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{
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uint32_t ie;
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@ -92,7 +92,7 @@ void dw_ace_irq_enable(const struct device *dev, uint32_t irq)
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ACE_INTC[i].irq_intmask_l &= ~BIT(ACE_IRQ_FROM_ZEPHYR(irq));
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}
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} else if ((irq & ~XTENSA_IRQ_NUM_MASK) == 0U) {
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z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
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xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
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}
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}
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@ -108,7 +108,7 @@ void dw_ace_irq_disable(const struct device *dev, uint32_t irq)
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ACE_INTC[i].irq_intmask_l |= BIT(ACE_IRQ_FROM_ZEPHYR(irq));
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}
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} else if ((irq & ~XTENSA_IRQ_NUM_MASK) == 0U) {
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z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
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xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
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}
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}
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@ -119,7 +119,7 @@ int dw_ace_irq_is_enabled(const struct device *dev, unsigned int irq)
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if (is_dw_irq(irq)) {
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return ACE_INTC[0].irq_inten_l & BIT(ACE_IRQ_FROM_ZEPHYR(irq));
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} else if ((irq & ~XTENSA_IRQ_NUM_MASK) == 0U) {
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return z_xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
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return xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
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}
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return false;
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@ -161,7 +161,7 @@ static int dw_ace_init(const struct device *dev)
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ARG_UNUSED(dev);
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IRQ_CONNECT(ACE_INTC_IRQ, 0, dwint_isr, 0, 0);
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z_xtensa_irq_enable(ACE_INTC_IRQ);
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xtensa_irq_enable(ACE_INTC_IRQ);
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return 0;
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}
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@ -324,9 +324,9 @@ void z_soc_irq_enable_disable(uint32_t irq, bool enable)
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if (irq_get_level(irq) == 1) {
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/* LEVEL 1 interrupts are DSP direct */
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if (enable) {
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z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
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xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
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} else {
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z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
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xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
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}
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return;
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}
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@ -375,7 +375,7 @@ int z_soc_irq_is_enabled(unsigned int irq)
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if (irq_get_level(irq) == 1) {
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/* LEVEL 1 interrupts are DSP direct */
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return z_xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
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return xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
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}
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parent_irq = irq_parent_level_2(irq);
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@ -449,7 +449,7 @@ static void irqsteer_enable_dispatchers(const struct device *dev)
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IRQSTEER_EnableMasterInterrupt(UINT_TO_IRQSTEER(cfg->regmap_phys),
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dispatcher->irq);
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z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(dispatcher->irq));
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xtensa_irq_enable(XTENSA_IRQ_NUMBER(dispatcher->irq));
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}
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}
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@ -13,6 +13,10 @@
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#define CONFIG_GEN_IRQ_START_VECTOR 0
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/**
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* @cond INTERNAL_HIDDEN
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*/
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/*
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* Call this function to enable the specified interrupts.
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*
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@ -42,6 +46,7 @@ static inline void z_xt_ints_off(unsigned int mask)
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__asm__ volatile("wsr.intenable %0; rsync" : : "r"(val));
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}
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/*
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* Call this function to set the specified (s/w) interrupt.
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*/
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@ -54,6 +59,10 @@ static inline void z_xt_set_intset(unsigned int arg)
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#endif
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}
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/**
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* INTERNAL_HIDDEN @endcond
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*/
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#ifdef CONFIG_MULTI_LEVEL_INTERRUPTS
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/* for _soc_irq_*() */
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@ -94,19 +103,29 @@ extern int z_soc_irq_connect_dynamic(unsigned int irq, unsigned int priority,
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#define CONFIG_NUM_IRQS XCHAL_NUM_INTERRUPTS
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#define arch_irq_enable(irq) z_xtensa_irq_enable(irq)
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#define arch_irq_disable(irq) z_xtensa_irq_disable(irq)
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#define arch_irq_enable(irq) xtensa_irq_enable(irq)
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#define arch_irq_disable(irq) xtensa_irq_disable(irq)
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#define arch_irq_is_enabled(irq) z_xtensa_irq_is_enabled(irq)
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#define arch_irq_is_enabled(irq) xtensa_irq_is_enabled(irq)
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#endif
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static ALWAYS_INLINE void z_xtensa_irq_enable(uint32_t irq)
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/**
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* @brief Enable interrupt on Xtensa core.
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*
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* @param irq Interrupt to be enabled.
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*/
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static ALWAYS_INLINE void xtensa_irq_enable(uint32_t irq)
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{
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z_xt_ints_on(1 << irq);
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}
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static ALWAYS_INLINE void z_xtensa_irq_disable(uint32_t irq)
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/**
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* @brief Disable interrupt on Xtensa core.
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*
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* @param irq Interrupt to be disabled.
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*/
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static ALWAYS_INLINE void xtensa_irq_disable(uint32_t irq)
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{
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z_xt_ints_off(1 << irq);
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}
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@ -131,7 +150,14 @@ static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
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return (key & 0xf) == 0; /* INTLEVEL field */
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}
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extern int z_xtensa_irq_is_enabled(unsigned int irq);
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/**
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* @brief Query if an interrupt is enabled on Xtensa core.
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*
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* @param irq Interrupt to be queried.
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*
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* @return True if interrupt is enabled, false otherwise.
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*/
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extern int xtensa_irq_is_enabled(unsigned int irq);
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#include <zephyr/irq.h>
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@ -159,7 +159,7 @@ void soc_start_core(int cpu_num)
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void soc_mp_startup(uint32_t cpu)
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{
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/* Must have this enabled always */
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z_xtensa_irq_enable(ACE_INTC_IRQ);
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xtensa_irq_enable(ACE_INTC_IRQ);
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#if CONFIG_ADSP_IDLE_CLOCK_GATING
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/* Disable idle power gating */
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@ -42,7 +42,7 @@ void z_soc_irq_enable(uint32_t irq)
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break;
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default:
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/* regular interrupt */
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z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
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xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
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return;
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}
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@ -55,7 +55,7 @@ void z_soc_irq_enable(uint32_t irq)
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* The specified interrupt is in CAVS interrupt controller.
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* So enable core interrupt first.
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*/
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z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
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xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
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/* Then enable the interrupt in CAVS interrupt controller */
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irq_enable_next_level(dev_cavs, CAVS_IRQ_NUMBER(irq));
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@ -80,7 +80,7 @@ void z_soc_irq_disable(uint32_t irq)
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break;
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default:
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/* regular interrupt */
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z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
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xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
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return;
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}
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@ -97,7 +97,7 @@ void z_soc_irq_disable(uint32_t irq)
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/* Then disable the parent IRQ if all children are disabled */
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if (!irq_is_enabled_next_level(dev_cavs)) {
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z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
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xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
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}
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}
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@ -121,7 +121,7 @@ int z_soc_irq_is_enabled(unsigned int irq)
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break;
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default:
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/* regular interrupt */
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ret = z_xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
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ret = xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
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goto out;
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}
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@ -25,7 +25,7 @@ void z_soc_irq_enable(uint32_t irq)
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/*
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* enable core interrupt
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*/
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z_xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
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xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
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}
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void z_soc_irq_disable(uint32_t irq)
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@ -33,7 +33,7 @@ void z_soc_irq_disable(uint32_t irq)
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/*
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* disable the interrupt in interrupt controller
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*/
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z_xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
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xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
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}
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int z_soc_irq_is_enabled(unsigned int irq)
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@ -41,7 +41,7 @@ int z_soc_irq_is_enabled(unsigned int irq)
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int ret = 0;
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/* regular interrupt */
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ret = z_xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
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ret = xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
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return ret;
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}
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