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soc: rt10xx: fix the sequence of Enet2 ref clk enablement

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This patch sets ENET2 ref clock to be generated by External OSC

ENET2 ref clock direction as output

ENET2 ref clk frequency to 50MHz

Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
This commit is contained in:
Sumit Batra 2023-06-04 23:56:09 +05:30 • committed by Mahesh Mahadevan
commit 0ae7010946
1 changed files with 12 additions and 0 deletions
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12
soc/arm/nxp_imx/rt/soc_rt10xx.c
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@ -66,7 +66,12 @@ const clock_enet_pll_config_t ethPllConfig = {
#else
.enableClkOutput25M = false,
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay)
.loopDivider = 1,
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay)
.loopDivider1 = 1,
#endif
};
#endif
@ -199,6 +204,13 @@ static ALWAYS_INLINE void clock_init(void)
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay) && CONFIG_NET_L2_ETHERNET
/* Set ENET2 ref clock to be generated by External OSC,*/
/* direction as output and frequency to 50MHz */
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2TxClkOutputDir |
kIOMUXC_GPR_ENET2RefClkMode, true);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) && CONFIG_USB_DC_NXP_EHCI
CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usb480M,
DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency));