arch/xtensa: clean up arch_cpu_idle function
Some workarounds were introduced for intel cavs2.5 platform bring up. It is not general so move them to platform code. Signed-off-by: Rander Wang <rander.wang@intel.com>
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3 changed files with 14 additions and 49 deletions
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@ -50,18 +50,6 @@ config XTENSA_ENABLE_BACKTRACE
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help
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Enable this config option to print backtrace on panic exception
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config XTENSA_CPU_IDLE_SPIN
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bool "Use busy loop for k_cpu_idle"
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help
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Use a spin loop instead of WAITI for the CPU idle state.
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config XTENSA_WAITI_BUG
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bool "Workaround sequence for WAITI bug on LX6"
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help
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SOF traditionally contains this workaround on its ADSP
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platforms which prefixes a WAITI entry with 128 NOP
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instructions followed by an ISYNC and EXTW.
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config XTENSA_SMALL_VECTOR_TABLE_ENTRY
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bool "Workaround for small vector table entries"
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help
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@ -6,48 +6,13 @@
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#include <zephyr/toolchain.h>
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#include <zephyr/tracing/tracing.h>
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/* xt-clang removes any NOPs more than 8. So we need to set
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* no optimization to avoid those NOPs from being removed.
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*
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* This function is simply enough and full of hand written
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* assembly that optimization is not really meaningful
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* anyway. So we can skip optimization unconditionally.
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* Re-evalulate its use and add #ifdef if this assumption
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* is no longer valid.
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*/
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__no_optimization
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#ifndef CONFIG_ARCH_CPU_IDLE_CUSTOM
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void arch_cpu_idle(void)
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{
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sys_trace_idle();
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/* Just spin forever with interrupts unmasked, for platforms
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* where WAITI can't be used or where its behavior is
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* complicated (Intel DSPs will power gate on idle entry under
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* some circumstances)
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*/
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if (IS_ENABLED(CONFIG_XTENSA_CPU_IDLE_SPIN)) {
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__asm__ volatile("rsil a0, 0");
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__asm__ volatile("loop_forever: j loop_forever");
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return;
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}
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/* Cribbed from SOF: workaround for a bug in some versions of
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* the LX6 IP. Preprocessor ugliness avoids the need to
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* figure out how to get the compiler to unroll a loop.
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*/
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if (IS_ENABLED(CONFIG_XTENSA_WAITI_BUG)) {
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#define NOP4 __asm__ volatile("nop; nop; nop; nop");
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#define NOP32 NOP4 NOP4 NOP4 NOP4 NOP4 NOP4 NOP4 NOP4
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#define NOP128() NOP32 NOP32 NOP32 NOP32
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NOP128();
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#undef NOP128
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#undef NOP32
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#undef NOP4
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__asm__ volatile("isync; extw");
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}
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__asm__ volatile ("waiti 0");
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}
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#endif
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void arch_cpu_atomic_idle(unsigned int key)
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{
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@ -113,4 +113,16 @@ config ADSP_IMR_CONTEXT_SAVE
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entering D3 state. Later this context can be used to FW restore
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when Host power up DSP again.
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config XTENSA_CPU_IDLE_SPIN
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bool "Use busy loop for k_cpu_idle"
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help
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Use a spin loop instead of WAITI for the CPU idle state.
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config XTENSA_WAITI_BUG
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bool "Workaround sequence for WAITI bug on LX6"
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help
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SOF traditionally contains this workaround on its ADSP
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platforms which prefixes a WAITI entry with 128 NOP
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instructions followed by an ISYNC and EXTW.
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endif # SOC_FAMILY_INTEL_ADSP
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