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dts: arm: Add support for STM32F722 SoC

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The STM32F722 is similar to the STM32F723, but lacks the latter's
more advanced USB PHY. Otherwise, they are virtually identical.

Signed-off-by: Evan Perry Grove <evan@4grove.com>
This commit is contained in:
Evan Perry Grove 2023-12-08 14:51:37 -06:00 • committed by Carles Cufí
commit a54a52b085
5 changed files with 91 additions and 40 deletions
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53
dts/arm/st/f7/stm32f722.dtsi Normal file
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@ -0,0 +1,53 @@
/*
* Copyright (c) 2023 Evan Perry Grove
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f7/stm32f7.dtsi>
/ {
/* 16KB ITCM @ 0x0, 64KB DTCM @ 0x20000000,
* 176KB SRAM1 @ 0x20010000, 16KB SRAM2 @ 0x2003C00
*/
sram0: memory@20010000 {
compatible = "mmio-sram";
reg = <0x20010000 DT_SIZE_K(192)>;
};
dtcm: memory@20000000 {
compatible = "zephyr,memory-region", "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(64)>;
zephyr,memory-region = "DTCM";
};
itcm: memory@0 {
compatible = "zephyr,memory-region", "arm,itcm";
reg = <0x00000000 DT_SIZE_K(16)>;
zephyr,memory-region = "ITCM";
};
soc {
compatible = "st,stm32f722", "st,stm32f7", "simple-bus";
sdmmc2: sdmmc@40011c00 {
compatible = "st,stm32-sdmmc";
reg = <0x40011c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>,
<&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>;
resets = <&rctl STM32_RESET(APB2, 7U)>;
interrupts = <103 0>;
status = "disabled";
};
};
die_temp: dietemp {
ts-cal1-addr = <0x1FF07A2C>;
ts-cal2-addr = <0x1FF07A2E>;
};
vref: vref {
vrefint-cal-addr = <0x1FF07A2A>;
};
};

18
dts/arm/st/f7/stm32f722Xe.dtsi Normal file
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@ -0,0 +1,18 @@
/*
* Copyright (c) 2023 Evan Perry Grove
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f7/stm32f722.dtsi>
/ {
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(512)>;
};
};
};
};

41
dts/arm/st/f7/stm32f723.dtsi
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@ -4,28 +4,9 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f7/stm32f7.dtsi>
#include <st/f7/stm32f722.dtsi>
/ {
/* 64KB DTCM @ 0x20000000, 176KB SRAM1 @ 0x20010000, 16KB SRAM2 @ 0x2003C00 */
sram0: memory@20010000 {
compatible = "mmio-sram";
reg = <0x20010000 DT_SIZE_K(192)>;
};
dtcm: memory@20000000 {
compatible = "zephyr,memory-region", "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(64)>;
zephyr,memory-region = "DTCM";
};
itcm: memory@0 {
compatible = "zephyr,memory-region", "arm,itcm";
reg = <0x00000000 DT_SIZE_K(16)>;
zephyr,memory-region = "ITCM";
};
soc {
compatible = "st,stm32f723", "st,stm32f7", "simple-bus";
@ -39,26 +20,6 @@
phys = <&usbphyc>;
maximum-speed = "high-speed";
};
sdmmc2: sdmmc@40011c00 {
compatible = "st,stm32-sdmmc";
reg = <0x40011c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>,
<&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>;
resets = <&rctl STM32_RESET(APB2, 7U)>;
interrupts = <103 0>;
status = "disabled";
};
};
vref: vref {
compatible = "st,stm32-vref";
vrefint-cal-addr = <0x1FF07A2A>;
};
die_temp: dietemp {
ts-cal1-addr = <0x1FF07A2C>;
ts-cal2-addr = <0x1FF07A2E>;
};
};

15
soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f722xx Normal file
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@ -0,0 +1,15 @@
# ST STM32F722XE Configuration options
#
# Copyright (c) 2023 Evan Perry Grove
#
# SPDX-License-Identifier: Apache-2.0
if SOC_STM32F722XX
config SOC
default "stm32f722xx"
config NUM_IRQS
default 104
endif # SOC_STM32F722XX

4
soc/arm/st_stm32/stm32f7/Kconfig.soc
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@ -3,12 +3,16 @@
# Copyright (c) 2018 Yurii Hamann
# Copyright (c) 2022, Rtone.
# Copyright (c) 2023, Rahul Arasikere.
# Copyright (c) 2023 Evan Perry Grove
# SPDX-License-Identifier: Apache-2.0
choice
prompt "STM32F7x MCU Selection"
depends on SOC_SERIES_STM32F7X
config SOC_STM32F722XX
bool "STM32F722XX"
config SOC_STM32F723XX
bool "STM32F723XX"