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xtensa: intel_adsp: fix a cache handling error

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.bss and .data are uncached in Zephyr builds for intel_adsp. No need
to try to manipulate cache of objects in those sections.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This commit is contained in:
Guennadi Liakhovetski 2024-01-12 14:14:46 +01:00 • committed by Carles Cufí
commit ca12fd13c6
2 changed files with 6 additions and 4 deletions
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2
drivers/power_domain/power_domain_intel_adsp.c
View file

@ -39,7 +39,7 @@ static int pd_intel_adsp_set_power_enable(struct pg_bits *bits, bool power_enabl
extern uint32_t g_key_read_holder;
if (bits->SPA_bit == INTEL_ADSP_HST_DOMAIN_BIT) {
volatile uint32_t *key_read_ptr = z_soc_uncached_ptr(&g_key_read_holder);
volatile uint32_t *key_read_ptr = &g_key_read_holder;
uint32_t key_value = *key_read_ptr;
if (key_value != INTEL_ADSP_ACE15_MAGIC_KEY)

8
soc/xtensa/intel_adsp/ace/multiprocessing.c
View file

@ -8,6 +8,7 @@
#include <zephyr/kernel.h>
#include <zephyr/sys/check.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/arch/xtensa/arch.h>
#include <zephyr/pm/pm.h>
#include <zephyr/pm/device_runtime.h>
@ -27,8 +28,8 @@
#define ACE_INTC_IRQ DT_IRQN(DT_NODELABEL(ace_intc))
#if CONFIG_ACE_VERSION_1_5
__aligned(CONFIG_DCACHE_LINE_SIZE) uint32_t g_key_read_holder;
__aligned(CONFIG_DCACHE_LINE_SIZE) unsigned int alignment_dummy[0];
/* .bss is uncached, we further check it below */
uint32_t g_key_read_holder;
#endif /* CONFIG_ACE_VERSION_1_5 */
static void ipc_isr(void *arg)
@ -93,8 +94,9 @@ void soc_mp_init(void)
/* Set the core 0 active */
soc_cpus_active[0] = true;
#if CONFIG_ACE_VERSION_1_5
__ASSERT(!arch_xtensa_is_ptr_cached(&g_key_read_holder),
"g_key_read_holder must be uncached");
g_key_read_holder = INTEL_ADSP_ACE15_MAGIC_KEY;
sys_cache_data_flush_range(&g_key_read_holder, sizeof(g_key_read_holder));
#endif /* CONFIG_ACE_VERSION_1_5 */
}